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GET /api/1.2/patches/2223448/?format=api
{ "id": 2223448, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223448/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-15-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-15-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:35", "name": "[v4,14/31] hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6cbd3aff55ff49c7af9805460e01fc4a1e17015e", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-15-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223448/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223448/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Fj8EnWrV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c111::9;\n envelope-from=skolothumtho@nvidia.com;\n helo=DM5PR21CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 14/31] hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region", "Date": "Wed, 15 Apr 2026 11:55:35 +0100", "Message-ID": "<20260415105552.622421-15-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3C:EE_|IA1PR12MB7493:EE_", "X-MS-Office365-Filtering-Correlation-Id": "71cb1a45-543a-472e-1a31-08de9addcf5e", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n w+on5BLn0gXC+J2tfxKW3jvJ87rHskEIs1DQeJVj0PhmCUMybpsoa1mcW7mtqagqEa5Wlvsv4itmrBNGOo4YxUol3jY11ItWRLxds4zNNydokSG82GKvq/+oDWwnurajaIzVmvcsUGizq1tk+IHQUTH8T/uvsS1YTrmRKsJJbcb4JMuT/sfrF1Pt5H8mxWq1ShzAcSGzohj/LE+rbyhP79BWBGI6ZgAwHz6f26zRSRUa/99tKF0kxWkjeQHcSsT42HCuPd+emsQjlualXa4edk3sYI1ZJJ87E3Bg6YRG45VA+T27JFOkLYCGZR7Eg4qnT2qARDgHr5yUZZQNRgDjBj5inPYB4S0AFUiD1Vs5hAHu9gu8QLPTRJ3jqgaiNeD4MTkIk2Jf5kLIluARaMcf12dZsBiuojfjKHCNrX9RhjjSERkH2M62UbP3Jhj26VZxVI2bvwVWH7xXuutp8dy1jshbphZT+8f5acMYU9loxV7xClD0HUOHmY1fM7nnkYROs4miaEMjixPt4pZDZNlVkIjHhZq8IGlrVgDKgG8D3TuIPgrq7VGlpcPKTV9oXccmZBUykKBZomXogrujTthP59t5poCQ+zKoUZ9KJljoTo42uTCNOgYvte1yh7HyAH87EbkM+q2XKPYCzW/xaFbvBU7fIdeQSjvCktyI7g2IgWSxa5soEjJINDE3G9rqM63ssrnz1SGgG/jBVpydemjkxrolIIG+bLMgdhl9oMXQOLg1KjblKwT2DvOoWULG9SZn2k0d5uZ+UK4eLr2mEJmq0Q==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(56012099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n SRrVXHtuL3JrdKoVgF4dbyqYECV9hwko0TLqthoTcK6BAP2boulHXSyQhQBnTEGzxnQSXvORMT5rcbZYakIPs8O4KGzHZOavgrfANcG1usGkepLutO9baP6sOTovTbc2Y+v2oMAeodA5w7rGMI6wNfgvslGZMBPJUis/4H/izNgq+MSbPm5DIWrKH3nUDW8NqJlKiudjPIetARaINlzaaanpfYEwOg0Ncc+cVJHZ3WVHJhru5NM6yERLXs16ZejiHDdiAOJOC1989tzrDb4ldYACm1apJx2MYw7Y7mDtrwKcSa5VOS9JtvXg/AzMMhDUAHNoKLmRTgjatrrYkWEcPVcO5U7lnJLP7LoYo5Bg31t8q9ymVwLPESoMcSt2itVc7G71AgiFFTrbnxlTw2UHufpiqnaVX169AvpSA0WNi7QFRfQ2nSwCv+RzD5+dvEbl", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:38.9866 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 71cb1a45-543a-472e-1a31-08de9addcf5e", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3C.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB7493", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nTegra241 CMDQV exposes control and status registers in the CMDQ-V\nConfig page (offset [0x0, 0x10000)) used to configure virtual command\nqueue allocation and interrupt behavior.\n\nAdd read/write emulation for the CMDQ-V Config region\n([CMDQV_BASE, CMDQV_CMDQ_BASE]), backed by a simple register cache.\nThis includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ\nallocation map and the VINTF0 related registers defined in the CMDQ-V\nConfig space. Only VINTF0 is supported; VINTF1-63 are not.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 127 +++++++++++++++++++++++++++++++\n hw/arm/tegra241-cmdqv.c | 163 ++++++++++++++++++++++++++++++++++++++--\n hw/arm/trace-events | 4 +\n 3 files changed, 288 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex fa0aa3ab04..965670066d 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -10,10 +10,14 @@\n #ifndef HW_ARM_TEGRA241_CMDQV_H\n #define HW_ARM_TEGRA241_CMDQV_H\n \n+#include \"hw/core/registerfields.h\"\n+\n #define CMDQV_VER 1\n #define CMDQV_NUM_CMDQ_LOG2 1\n #define CMDQV_NUM_SID_PER_VI_LOG2 4\n \n+#define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2)\n+\n /*\n * Tegra241 CMDQV MMIO layout (64KB pages)\n *\n@@ -31,8 +35,131 @@ typedef struct Tegra241CMDQV {\n MemoryRegion mmio_cmdqv;\n qemu_irq irq;\n IOMMUFDVeventq *veventq;\n+\n+ /* Register Cache */\n+ uint32_t config;\n+ uint32_t param;\n+ uint32_t status;\n+ uint32_t vi_err_map[2];\n+ uint32_t vi_int_mask[2];\n+ uint32_t cmdq_err_map[4];\n+ uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ];\n+ uint32_t vintf_config;\n+ uint32_t vintf_status;\n+ uint32_t vintf_sid_match[16];\n+ uint32_t vintf_sid_replace[16];\n+ uint32_t vintf_cmdq_err_map[4];\n } Tegra241CMDQV;\n \n+/* CMDQ-V Config page registers (offset 0x00000) */\n+REG32(CONFIG, 0x0)\n+FIELD(CONFIG, CMDQV_EN, 0, 1)\n+FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3)\n+FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8)\n+FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8)\n+FIELD(CONFIG, CONS_DRAM_EN, 20, 1)\n+\n+REG32(PARAM, 0x4)\n+FIELD(PARAM, CMDQV_VER, 0, 4)\n+FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4)\n+FIELD(PARAM, CMDQV_NUM_VI_LOG2, 8, 4)\n+FIELD(PARAM, CMDQV_NUM_SID_PER_VI_LOG2, 12, 4)\n+\n+REG32(STATUS, 0x8)\n+FIELD(STATUS, CMDQV_ENABLED, 0, 1)\n+\n+/* SMMU_CMDQV_VI_ERR_MAP_0/1 definitions */\n+#define A_VI_ERR_MAP_0 0x14\n+#define A_VI_ERR_MAP_1 0x18\n+#define V_VI_ERR_MAP_NO_ERROR (0)\n+#define V_VI_ERR_MAP_ERROR (1)\n+\n+/* SMMU_CMDQV_VI_INT_MASK_0/1 definitions */\n+#define A_VI_INT_MASK 0x1c\n+#define A_VI_INT_MASK_1 0x20\n+#define V_VI_INT_MASK_NOT_MASKED (0)\n+#define V_VI_INT_MASK_MASKED (1)\n+\n+/* SMMU_CMDQV_CMDQ_ERR_MAP_0-3 definitions */\n+#define A_CMDQ_ERR_MAP_0 0x24\n+#define A_CMDQ_ERR_MAP_1 0x28\n+#define A_CMDQ_ERR_MAP_2 0x2c\n+#define A_CMDQ_ERR_MAP_3 0x30\n+\n+/*\n+ * CMDQ_ALLOC_MAP: one entry per physical VCMDQ. Hardware supports up to 128\n+ * entries (CMDQV_NUM_CMDQ_LOG2=7), but QEMU only exposes\n+ * TEGRA241_CMDQV_MAX_CMDQ (=2) VCMDQs per VM so only entries 0 and 1 are\n+ * defined here.\n+ */\n+/* 2 identical register entries */\n+#define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \\\n+ REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \\\n+ FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \\\n+ FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \\\n+ FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6)\n+\n+SMMU_CMDQV_CMDQ_ALLOC_MAP_(0)\n+SMMU_CMDQV_CMDQ_ALLOC_MAP_(1)\n+\n+\n+/* Only VINTF0 is exposed to the guest; vintf = 0 */\n+#define SMMU_CMDQV_VINTFi_CONFIG_(vi) \\\n+ REG32(VINTF##vi##_CONFIG, 0x1000 + vi * 0x100) \\\n+ FIELD(VINTF##vi##_CONFIG, ENABLE, 0, 1) \\\n+ FIELD(VINTF##vi##_CONFIG, VMID, 1, 16) \\\n+ FIELD(VINTF##vi##_CONFIG, HYP_OWN, 17, 1)\n+\n+SMMU_CMDQV_VINTFi_CONFIG_(0)\n+\n+#define SMMU_CMDQV_VINTFi_STATUS_(vi) \\\n+ REG32(VINTF##vi##_STATUS, 0x1004 + vi * 0x100) \\\n+ FIELD(VINTF##vi##_STATUS, ENABLE_OK, 0, 1) \\\n+ FIELD(VINTF##vi##_STATUS, STATUS, 1, 3) \\\n+ FIELD(VINTF##vi##_STATUS, VI_NUM_LVCMDQ, 16, 8)\n+\n+SMMU_CMDQV_VINTFi_STATUS_(0)\n+\n+#define V_VINTF_STATUS_NO_ERROR (0 << 1)\n+#define V_VINTF_STATUS_VCMDQ_ERROR (1 << 1)\n+\n+/*\n+ * SID_MATCH/SID_REPLACE: 16 entries per VINTF (CMDQV_NUM_SID_PER_VI_LOG2=4).\n+ * vintf = 0, 16 identical register entries\n+ */\n+#define SMMU_CMDQV_VINTFi_SID_MATCH_(vi, j) \\\n+ REG32(VINTF##vi##_SID_MATCH_##j, 0x1040 + j * 4 + vi * 0x100) \\\n+ FIELD(VINTF##vi##_SID_MATCH_##j, ENABLE, 0, 1) \\\n+ FIELD(VINTF##vi##_SID_MATCH_##j, VIRT_SID, 1, 20)\n+\n+SMMU_CMDQV_VINTFi_SID_MATCH_(0, 0)\n+/* Omitting [0][1~14] as not being directly called */\n+SMMU_CMDQV_VINTFi_SID_MATCH_(0, 15)\n+\n+/* vintf = 0, 16 identical register entries */\n+#define SMMU_CMDQV_VINTFi_SID_REPLACE_(vi, j) \\\n+ REG32(VINTF##vi##_SID_REPLACE_##j, 0x1080 + j * 4 + vi * 0x100) \\\n+ FIELD(VINTF##vi##_SID_REPLACE_##j, PHYS_SID, 0, 20)\n+\n+SMMU_CMDQV_VINTFi_SID_REPLACE_(0, 0)\n+/* Omitting [0][1~14] as not being directly called */\n+SMMU_CMDQV_VINTFi_SID_REPLACE_(0, 15)\n+\n+/*\n+ * LVCMDQ_ERR_MAP: hardware defines 4 registers per VINTF (offset\n+ * 0x10c0..0x10cc), each covering 32 logical VCMDQs. All 4 are accessible\n+ * by the guest. With TEGRA241_CMDQV_MAX_CMDQ=2 only MAP_0 bits [1:0]\n+ * carry meaningful error state; MAP_1..MAP_3 always read as 0.\n+ * vintf = 0, 4 identical register entries\n+ */\n+#define SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(vi, j) \\\n+ REG32(VINTF##vi##_LVCMDQ_ERR_MAP_##j, 0x10c0 + j * 4 + vi * 0x100) \\\n+ FIELD(VINTF##vi##_LVCMDQ_ERR_MAP_##j, LVCMDQ_ERR_MAP, 0, 32)\n+\n+SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 0)\n+/* MAP_1 and MAP_2 omitted; not referenced directly */\n+SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 3)\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 2f1084b55f..3b08ed0ff3 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -8,19 +8,170 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n \n #include \"hw/arm/smmuv3.h\"\n #include \"smmuv3-accel.h\"\n #include \"tegra241-cmdqv.h\"\n+#include \"trace.h\"\n \n-static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned size)\n+static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n+ hwaddr offset)\n {\n- return 0;\n+ int i;\n+\n+ switch (offset) {\n+ case A_VINTF0_CONFIG:\n+ return cmdqv->vintf_config;\n+ case A_VINTF0_STATUS:\n+ return cmdqv->vintf_status;\n+ case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15:\n+ i = (offset - A_VINTF0_SID_MATCH_0) / 4;\n+ return cmdqv->vintf_sid_match[i];\n+ case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15:\n+ i = (offset - A_VINTF0_SID_REPLACE_0) / 4;\n+ return cmdqv->vintf_sid_replace[i];\n+ case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n+ i = (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4;\n+ return cmdqv->vintf_cmdq_err_map[i];\n+ default:\n+ /*\n+ * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) are\n+ * filter config and filter data registers. They are not required for\n+ * normal VINTF operation and are not emulated.\n+ */\n+ qemu_log_mask(LOG_UNIMP, \"%s unhandled read access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset);\n+ return 0;\n+ }\n+}\n+\n+static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv,\n+ hwaddr offset, uint64_t value)\n+{\n+ int i;\n+\n+ switch (offset) {\n+ case A_VINTF0_CONFIG:\n+ /*\n+ * Mask out HYP_OWN on guest writes. This bit selects Hypervisor (1) vs\n+ * Guest (0) ownership of the CMDQ. Force it to 0 so the VINTF always\n+ * remains guest-owned.\n+ */\n+ value &= ~R_VINTF0_CONFIG_HYP_OWN_MASK;\n+\n+ cmdqv->vintf_config = value;\n+ if (value & R_VINTF0_CONFIG_ENABLE_MASK) {\n+ cmdqv->vintf_status |= R_VINTF0_STATUS_ENABLE_OK_MASK;\n+ } else {\n+ cmdqv->vintf_status &= ~R_VINTF0_STATUS_ENABLE_OK_MASK;\n+ }\n+ break;\n+ case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15:\n+ i = (offset - A_VINTF0_SID_MATCH_0) / 4;\n+ cmdqv->vintf_sid_match[i] = value;\n+ break;\n+ case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15:\n+ i = (offset - A_VINTF0_SID_REPLACE_0) / 4;\n+ cmdqv->vintf_sid_replace[i] = value;\n+ break;\n+ default:\n+ /*\n+ * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) are\n+ * filter config and filter data registers. They are not required for\n+ * normal VINTF operation and are not emulated.\n+ */\n+ qemu_log_mask(LOG_UNIMP, \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset);\n+ return;\n+ }\n+}\n+\n+static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset,\n+ unsigned size)\n+{\n+ Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n+ uint64_t val = 0;\n+\n+ if (offset >= TEGRA241_CMDQV_IO_LEN) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s offset 0x%\" PRIx64 \" off limit (0x%x)\\n\", __func__,\n+ offset, TEGRA241_CMDQV_IO_LEN);\n+ goto out;\n+ }\n+\n+ switch (offset) {\n+ case A_CONFIG:\n+ val = cmdqv->config;\n+ break;\n+ case A_PARAM:\n+ val = cmdqv->param;\n+ break;\n+ case A_STATUS:\n+ val = cmdqv->status;\n+ break;\n+ case A_VI_ERR_MAP_0 ... A_VI_ERR_MAP_1:\n+ val = cmdqv->vi_err_map[(offset - A_VI_ERR_MAP_0) / 4];\n+ break;\n+ case A_VI_INT_MASK ... A_VI_INT_MASK_1:\n+ val = cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4];\n+ break;\n+ case A_CMDQ_ERR_MAP_0 ... A_CMDQ_ERR_MAP_3:\n+ val = cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP_0) / 4];\n+ break;\n+ case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1:\n+ val = cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4];\n+ break;\n+ case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n+ val = tegra241_cmdqv_config_vintf_read(cmdqv, offset);\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"%s unhandled read access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset);\n+ }\n+\n+out:\n+ trace_tegra241_cmdqv_read_mmio(offset, val, size);\n+ return val;\n }\n \n-static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value,\n- unsigned size)\n+static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n+ uint64_t value, unsigned size)\n {\n+ Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n+\n+ if (offset >= TEGRA241_CMDQV_IO_LEN) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s offset 0x%\" PRIx64 \" off limit (0x%x)\\n\", __func__,\n+ offset, TEGRA241_CMDQV_IO_LEN);\n+ goto out;\n+ }\n+\n+ switch (offset) {\n+ case A_CONFIG:\n+ cmdqv->config = value;\n+ if (value & R_CONFIG_CMDQV_EN_MASK) {\n+ cmdqv->status |= R_STATUS_CMDQV_ENABLED_MASK;\n+ } else {\n+ cmdqv->status &= ~R_STATUS_CMDQV_ENABLED_MASK;\n+ }\n+ break;\n+ case A_VI_INT_MASK ... A_VI_INT_MASK_1:\n+ cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4] = value;\n+ break;\n+ case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1:\n+ cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] = value;\n+ break;\n+ case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n+ tegra241_cmdqv_config_vintf_write(cmdqv, offset, value);\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset);\n+ }\n+\n+out:\n+ trace_tegra241_cmdqv_write_mmio(offset, value, size);\n }\n \n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n@@ -84,8 +235,8 @@ static void tegra241_cmdqv_reset(SMMUv3State *s)\n }\n \n static const MemoryRegionOps mmio_cmdqv_ops = {\n- .read = tegra241_cmdqv_read,\n- .write = tegra241_cmdqv_write,\n+ .read = tegra241_cmdqv_read_mmio,\n+ .write = tegra241_cmdqv_write_mmio,\n .endianness = DEVICE_LITTLE_ENDIAN,\n };\n \ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex 3457536fb0..8c61d66a26 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -72,6 +72,10 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid) \"devfn=0x%x (idev dev\n smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1, uint64_t ste_0) \"vSID=0x%x hwpt_id=0x%x ste=%\"PRIx64\":%\"PRIx64\n smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) \"vSID=0x%x ste type=%s hwpt_id=0x%x\"\n \n+# tegra241-cmdqv\n+tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n+tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n+\n # strongarm.c\n strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) \"%s speed=%d parity=%c data=%d stop=%d\"\n strongarm_ssp_read_underrun(void) \"SSP rx underrun\"\n", "prefixes": [ "v4", "14/31" ] }