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GET /api/1.2/patches/2223442/?format=api
{ "id": 2223442, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223442/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-12-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-12-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:32", "name": "[v4,11/31] hw/arm/tegra241-cmdqv: Implement CMDQV init", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d66aa3f783c952206cc056426b21d8e892501d18", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-12-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223442/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223442/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=o7MP/bJE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 11/31] hw/arm/tegra241-cmdqv: Implement CMDQV init", "Date": "Wed, 15 Apr 2026 11:55:32 +0100", "Message-ID": "<20260415105552.622421-12-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3F:EE_|SA1PR12MB8164:EE_", "X-MS-Office365-Filtering-Correlation-Id": "743ef4d7-eea4-402f-3860-08de9addcb59", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|36860700016|376014|82310400026|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n mxYAwYtE2aXQ8PPG9Tksod7rkIDsIcexUDiv1GAhh0ROwxDKdi8OSzOUXazlB4Gn/fqCHiJRAOr/FtRSnjxyeD3w1t/oL87Si6KnIh1ABjI/oxd+p4Neut7jCNCpcL6JRO080PTxvM2aggEBHiKiv2eHFf/4JeSiU7MFmPo/MZcG5jQwRdgCFofrgzZ4KYGeGZD/IoFvVeQPychMRguG9FNCg4Km9v1lEmPWadG8rPSnTzW0yOQRQ+5gR/YOSrU+G5uuP7qFQvZudeK4xgLrjkr4fFDuhwmlc2HoFrCEDX63HdqYcTfOsXXHHD/ZM8TwoTd96NnDOVuPGN2CCWK+MgnUhmIWt/RA5NymvnZkB3U5j7zKdWFDyJeClxaZzXbP2Dvbqkegftx+KOeFPwTwFFDIa4/yVdipRIj0ro6SC5qi7aC0wIMvsh3LV5jNrmHEV2klLyy16YE6sxH+hjYKeVjBwEEmEhrWMKKGuzlvMooTThaGGl86gb+KCCNOv7twqPkTITNvCmDTZxnjGJ57OtnQbtwj96tp7pUIE7dpYeF548sxRISAdiyStQBnDncNA5dMsZM8S52+CWgQLU5POxlDjnoZ44bJiO4DOCWyJWTbAeShSKsfGnhPqDNCpWcYQoOPc0sYA0L9E+8jzR72CNZlVzxVjPC1X8zHRsoVMWGQhmGzc+G6Q+1a4q7I6tFwRCCeYKxzGK1r3L351/FBS2LtVL4NtwYAdgMhs5sFjEwKJHrPuTfw51SG+BAuYaz6G1QTI95VkeYw1oSSftvlIw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(18002099003)(56012099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n cGDXOueAWGQcUrZij9AU07nPrZON44xy6kRXLPazlmdA13t614hbmdmDPkmy5PkVtHNTSsTmrjuZRoG/g61lvsSK3rt/sQGSNelnYmjOl9OqI7tq7yl6lhOSCzlRwsjjFlEEwOGup+AVZTZyYhOTklkCKuLHAoG6FRKQCrtpzNBRmx7dLdl1N3bq08PYwRERplhEiewATT2iQQCyLAnOoxphL0FYUb3NzHG+HFA6B9EkJi/DGQUYsnoTvvlA4HcrN7s71VWfWS9cjJnTYphpkt4LVyiz3kU438VUDbBGNPU8ie6WMkn6fKIrWkfE5GirCPFcDP+6c+kCRQU4V+4axozz1usXMAvHTTWzNFzkmVwZQdIgz0pVdIOrXObhMldjYY2ktSvY911qqCYUsFc+iTutAVlxmssqRrl37+TEbAX5hZuBaq0n2kwjVyRsM43W", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:32.1897 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 743ef4d7-eea4-402f-3860-08de9addcb59", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3F.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8164", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nTegra241 CMDQV extends SMMUv3 with support for virtual command queues\n(VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split\ninto 64KB pages:\n\n0x00000 (CMDQ-V Config page)\n0x10000 (CMDQ-V CMDQ Page0)\n0x20000 (CMDQ-V CMDQ Page1)\n0x30000 (Virtual Interface Page0)\n0x40000 (Virtual Interface Page1)\n\nThis patch wires up the Tegra241 CMDQV init callback and allocates\nvendor-specific CMDQV state. The state pointer is stored in\nSMMUv3AccelState for use by subsequent CMDQV operations.\n\nThe CMDQV MMIO region and a dedicated IRQ line are registered with the\nSMMUv3 device. The MMIO read/write handlers are currently stubs and will\nbe implemented in later patches.\n\nThe CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF\nerror conditions. This patch only registers the IRQ line. Interrupt\ngeneration and propagation to the guest will be added in a subsequent\npatch.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nCo-developed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 1 +\n hw/arm/tegra241-cmdqv.h | 18 ++++++++++++++++++\n hw/arm/tegra241-cmdqv.c | 30 ++++++++++++++++++++++++++++--\n 3 files changed, 47 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 86301afcb4..28bceca061 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -45,6 +45,7 @@ typedef struct SMMUv3AccelState {\n bool auto_mode;\n bool auto_finalised;\n const SMMUv3AccelCmdqvOps *cmdqv_ops;\n+ void *cmdqv; /* vendor specific CMDQV state */\n } SMMUv3AccelState;\n \n typedef struct SMMUS1Hwpt {\ndiff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nindex c1866084f8..2a34a4b6b4 100644\n--- a/hw/arm/tegra241-cmdqv.h\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -14,6 +14,24 @@\n #define CMDQV_NUM_CMDQ_LOG2 1\n #define CMDQV_NUM_SID_PER_VI_LOG2 4\n \n+/*\n+ * Tegra241 CMDQV MMIO layout (64KB pages)\n+ *\n+ * 0x00000 (CMDQ-V Config page)\n+ * 0x10000 (CMDQ-V CMDQ Page0)\n+ * 0x20000 (CMDQ-V CMDQ Page1)\n+ * 0x30000 (Virtual Interface Page0)\n+ * 0x40000 (Virtual Interface Page1)\n+ */\n+#define TEGRA241_CMDQV_IO_LEN 0x50000\n+\n+typedef struct Tegra241CMDQV {\n+ struct iommu_viommu_tegra241_cmdqv cmdqv_data;\n+ SMMUv3AccelState *s_accel;\n+ MemoryRegion mmio_cmdqv;\n+ qemu_irq irq;\n+} Tegra241CMDQV;\n+\n const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n \n #endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 3a19a1af56..ccd3c6d275 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -13,6 +13,16 @@\n #include \"smmuv3-accel.h\"\n #include \"tegra241-cmdqv.h\"\n \n+static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned size)\n+{\n+ return 0;\n+}\n+\n+static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t value,\n+ unsigned size)\n+{\n+}\n+\n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n {\n }\n@@ -29,10 +39,26 @@ static void tegra241_cmdqv_reset(SMMUv3State *s)\n {\n }\n \n+static const MemoryRegionOps mmio_cmdqv_ops = {\n+ .read = tegra241_cmdqv_read,\n+ .write = tegra241_cmdqv_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+};\n+\n static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp)\n {\n- error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n- return false;\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(OBJECT(s));\n+ SMMUv3AccelState *accel = s->s_accel;\n+ Tegra241CMDQV *cmdqv;\n+\n+ cmdqv = g_new0(Tegra241CMDQV, 1);\n+ memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, cmdqv,\n+ \"tegra241-cmdqv\", TEGRA241_CMDQV_IO_LEN);\n+ sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv);\n+ sysbus_init_irq(sbd, &cmdqv->irq);\n+ cmdqv->s_accel = accel;\n+ accel->cmdqv = cmdqv;\n+ return true;\n }\n \n static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n", "prefixes": [ "v4", "11/31" ] }