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GET /api/1.2/patches/2223441/?format=api
{ "id": 2223441, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-25-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-25-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:45", "name": "[v4,24/31] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "45218f71ea4962f5175802d06593a6ab30fbbaf7", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-25-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223441/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223441/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=QUrJfJZ7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c005::5;\n envelope-from=skolothumtho@nvidia.com;\n helo=CO1PR03CU002.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 24/31] hw/arm/tegra241-cmdqv: Read and propagate Tegra241\n CMDQV errors", "Date": "Wed, 15 Apr 2026 11:55:45 +0100", "Message-ID": "<20260415105552.622421-25-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n 8TIVje+RjQTpGtYodD7+8bPnsdDwwflA+z4i85PrBwQJ1YSc3PeH07HYlcZiuE2TXn2Tper2A4GOK0e5zYuVmodZr6hI2Ej2jVMFWHgLHUCAaxB4MlQlP+SJSD4X+Dob0BSuueSWDc0s1pAEKzFgiptC31lrRNwU2jWWum89j/SuK16LADHsX9hiVcXwSm+30QzngxD3rm/DEHQtGr0OvgnYtwqKx8phPNNlot+sQd3Pi0CEooTKcqdAfgP3lN6ek8V6rNep7dyCB5XJigMYwq9t4U+aSej56Uv0ei8oK0DDb1bv6tfEPx+iMBvPE0kVUw1Tqzz6mLmq4jdmeLAFWNqDV39Z+PFhuDdAFOsDFaehZdmaPeorPgJgPwZeGQJvmL3mOrOkVqcOMnJ2d0F2S822/TFtFSr94IuLCxg9dX7p1oiVPvGDM//oquzuTIn4", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:58:21.4955 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 903e115c-6f98-4715-5004-08de9adde8bb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3D.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB5653", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Install an event handler on the CMDQV vEVENTQ fd to read and propagate\nhost received CMDQV errors to the guest.\n\nThe handler runs in QEMU’s main loop, using a non-blocking fd registered\nvia qemu_set_fd_handler().\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.c | 55 +++++++++++++++++++++++++++++++++++++++++\n hw/arm/trace-events | 1 +\n 2 files changed, 56 insertions(+)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex bf989dd51f..9c2fc02b92 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -11,6 +11,7 @@\n #include \"qemu/log.h\"\n \n #include \"hw/arm/smmuv3.h\"\n+#include \"hw/core/irq.h\"\n #include \"smmuv3-accel.h\"\n #include \"tegra241-cmdqv.h\"\n #include \"trace.h\"\n@@ -534,6 +535,43 @@ out:\n trace_tegra241_cmdqv_write_mmio(offset, value, size);\n }\n \n+static void tegra241_cmdqv_event_read(void *opaque)\n+{\n+ Tegra241CMDQV *cmdqv = opaque;\n+ IOMMUFDVeventq *veventq = cmdqv->veventq;\n+ struct {\n+ struct iommufd_vevent_header hdr;\n+ struct iommu_vevent_tegra241_cmdqv vevent;\n+ } buf;\n+ Error *local_err = NULL;\n+\n+ if (!smmuv3_accel_event_read_validate(veventq,\n+ IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV,\n+ &buf, sizeof(buf), &local_err)) {\n+ warn_report_err_once(local_err);\n+ return;\n+ }\n+\n+ if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) {\n+ cmdqv->vintf_cmdq_err_map[0] =\n+ buf.vevent.lvcmdq_err_map[0] & 0xffffffff;\n+ cmdqv->vintf_cmdq_err_map[1] =\n+ (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff;\n+ cmdqv->vintf_cmdq_err_map[2] =\n+ buf.vevent.lvcmdq_err_map[1] & 0xffffffff;\n+ cmdqv->vintf_cmdq_err_map[3] =\n+ (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff;\n+ for (int i = 0; i < 4; i++) {\n+ cmdqv->cmdq_err_map[i] = cmdqv->vintf_cmdq_err_map[i];\n+ }\n+ cmdqv->vi_err_map[0] |= 0x1;\n+ qemu_irq_pulse(cmdqv->irq);\n+ trace_tegra241_cmdqv_err_map(\n+ cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2],\n+ cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]);\n+ }\n+}\n+\n static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n {\n SMMUv3AccelState *accel = s->s_accel;\n@@ -545,6 +583,7 @@ static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n return;\n }\n if (veventq) {\n+ qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL);\n close(veventq->veventq_fd);\n iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id);\n g_free(veventq);\n@@ -560,6 +599,7 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Tegra241CMDQV *cmdqv = s->s_accel->cmdqv;\n uint32_t viommu_id, veventq_id, veventq_fd;\n IOMMUFDVeventq *veventq;\n+ int flags;\n \n if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid,\n IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV,\n@@ -577,14 +617,29 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_viommu;\n }\n \n+ flags = fcntl(veventq_fd, F_GETFL);\n+ if (flags < 0) {\n+ error_setg(errp, \"Failed to get flags for vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+ if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) {\n+ error_setg(errp, \"Failed to set O_NONBLOCK on vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+\n veventq = g_new(IOMMUFDVeventq, 1);\n veventq->veventq_id = veventq_id;\n veventq->veventq_fd = veventq_fd;\n cmdqv->veventq = veventq;\n \n+ /* Set up event handler for veventq fd */\n+ qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv);\n *out_viommu_id = viommu_id;\n return true;\n \n+free_veventq:\n+ close(veventq_fd);\n+ iommufd_backend_free_id(idev->iommufd, veventq_id);\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu_id);\n return false;\ndiff --git a/hw/arm/trace-events b/hw/arm/trace-events\nindex 8c61d66a26..fd6441bfa7 100644\n--- a/hw/arm/trace-events\n+++ b/hw/arm/trace-events\n@@ -75,6 +75,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_id) \"vS\n # tegra241-cmdqv\n tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) \"offset: 0x%\"PRIx64\" val: 0x%\"PRIx64\" size: 0x%x\"\n+tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32_t map0) \"hw irq received. error (hex) maps: %04X:%04X:%04X:%04X\"\n \n # strongarm.c\n strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) \"%s speed=%d parity=%c data=%d stop=%d\"\n", "prefixes": [ "v4", "24/31" ] }