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GET /api/1.2/patches/2223440/?format=api
{ "id": 2223440, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223440/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-17-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-17-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:37", "name": "[v4,16/31] hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4299c38b8d51c839bb65e7c606e2b6412f395883", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-17-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223440/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223440/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=T2ofGS+Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c107::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=PH8PR06CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 16/31] hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes", "Date": "Wed, 15 Apr 2026 11:55:37 +0100", "Message-ID": "<20260415105552.622421-17-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3B:EE_|LV2PR12MB5941:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f4740af8-16e1-4c84-9c15-08de9addd56c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n usKKRnCpa548y9jgfLS8sa8mRS3Qff6pCQ4OH68dYjcR4kxjGELGQtAY/C2h5GYCRqAvnWKmIlAcMQEv0NndaD5Ve7aIM2YFCTm+TlqTEsREwUmtHF1WPZPl/YvFrApA5CvdyTy5ek2IHB+uXrQaFm7K+lj+SS5v+vk4duXeZcXHiSG9i+tvmE6Mpw/a+G073ESXMMv4Zy74zugeHWqYgxhjuhzHSV+pACLruC5A4sK2s42VqWtBINib8SzUHHogI7s5+c725VkYdp37Yys7QOAicErENaMYPwHzI6x+KEhzJBsFWvCpANFe3Feu+6BU1wvgt1NMQJmkcPNPHQVlerqkfbFwH/MB9w7Jy2JDvWHXG+9JM72k0TYKjvjU01o2GVo7fa4wjkrhuPJIGIyLn59SmYBsXuBGRHk51L5ngUYnzU4XNBindLJdaRsckDRHRrtPJTn2tQGlL4P4Zxf2tEtfKj63+hTwGU9nZfXa7Y84lgRtyGfQoHdjdwebmDuYmdFJG/Vbo7jK8tubyLttcBwdXG4n5YziU21FyB5uc0snKs2HF022S1RhJjYF5p/QuAUlQeS7xswsO3q/KkuP99mgn5Nwpv5a4OqIIEOUFUbKMQmVRz3jSFTJ005Qffqy1MlfhYC0qIxpNZ7My1fOyuwJM8/F42k3Wg3MkgcwkKc2VFdsOZkHhxsbOM+rjfXpE5NzAQojvSrZ7nDV12F9FBjj/8l9WqKaT9tqFefR+3wMF1fFAR68nZsxToxuujQUw7yKxCmaDU/Ioe9OmQLqNw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(18002099003)(22082099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n e744lZ+WgyHXEqVywTjlfiPu9ScItBiRSFb+epN60jhMWBF3jFvhAw5FRaME3MwQtZIHEaBodmRRb9Wnc4bpammGjHobWRq5YLxCYqxcQmzWxacsTv5cf7OuzMxcgMKa9ENBNutN23KtYzNQ+j4As4CJpDbJJKyD/P3Vy7a4Q0QfZdboVUhi/LexN8VyaW9zezivOqgcOn+RTFmHrpqdT3VkRPJM+Vba9aKFKP4kKSTATd2u8eVKetIo/2RjQK1FOXdquKU1QAr418ajWb+cLpkBfNo5n06Dtazb+ofRQodCzl9HA3Bp8DQ2l9IKjNjBa0sX0BRNAFc68rQLbVqN/Sd/m+3MYDrbdK84eRCJP90hgIQxvYBoKlRWSBEbc+BoFkCWJt4IxH0fQZ5Fuwth8yB3rRrZnXJ3sf6ynXgooMm2N38gFQnOfxGZ6oB2pQMN", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:49.0844 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f4740af8-16e1-4c84-9c15-08de9addd56c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5941", "X-Spam_score_int": "-25", "X-Spam_score": "-2.6", "X-Spam_bar": "--", "X-Spam_report": "(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nThis is the write side counterpart of the VCMDQ read emulation. Add write\nhandling for both CMDQV_CMDQ_BASE and CMDQV_VI_CMDQ_BASE apertures using\nthe same index decoding and VINTF-to-VCMDQ translation logic as the read\npath.\n\nVINTF aperture writes are translated to their CMDQV_CMDQ_BASE equivalent\nand update the same cached state. Page1 registers (BASE, CONS_INDX_BASE)\nalways update the cache. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are\nwired up in a subsequent patch, Page0 register writes will be forwarded\nto the hardware-backed mmap'd page.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.c | 99 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 99 insertions(+)", "diff": "diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nindex 35e6f0bbd6..d4ba2ada92 100644\n--- a/hw/arm/tegra241-cmdqv.c\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -55,6 +55,70 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n }\n }\n \n+/*\n+ * Write a VCMDQ register using VCMDQ0_* offsets.\n+ *\n+ * The caller normalizes the MMIO offset such that @offset0 always refers\n+ * to a VCMDQ0_* register, while @index selects the VCMDQ instance.\n+ */\n+static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0,\n+ int index, uint64_t value,\n+ unsigned size)\n+{\n+ switch (offset0) {\n+ case A_VCMDQ0_CONS_INDX:\n+ cmdqv->vcmdq_cons_indx[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_PROD_INDX:\n+ cmdqv->vcmdq_prod_indx[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_CONFIG:\n+ if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) {\n+ cmdqv->vcmdq_status[index] |= R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK;\n+ } else {\n+ cmdqv->vcmdq_status[index] &= ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MASK;\n+ }\n+ cmdqv->vcmdq_config[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_GERRORN:\n+ cmdqv->vcmdq_gerrorn[index] = (uint32_t)value;\n+ return;\n+ case A_VCMDQ0_BASE_L:\n+ if (size == 8) {\n+ cmdqv->vcmdq_base[index] = value;\n+ } else {\n+ cmdqv->vcmdq_base[index] =\n+ (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) |\n+ (value & 0xffffffffULL);\n+ }\n+ return;\n+ case A_VCMDQ0_BASE_H:\n+ cmdqv->vcmdq_base[index] =\n+ (cmdqv->vcmdq_base[index] & 0xffffffffULL) |\n+ ((uint64_t)value << 32);\n+ return;\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_L:\n+ if (size == 8) {\n+ cmdqv->vcmdq_cons_indx_base[index] = value;\n+ } else {\n+ cmdqv->vcmdq_cons_indx_base[index] =\n+ (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffff00000000ULL) |\n+ (value & 0xffffffffULL);\n+ }\n+ return;\n+ case A_VCMDQ0_CONS_INDX_BASE_DRAM_H:\n+ cmdqv->vcmdq_cons_indx_base[index] =\n+ (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffffULL) |\n+ ((uint64_t)value << 32);\n+ return;\n+ default:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n+ __func__, offset0);\n+ return;\n+ }\n+}\n+\n static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv,\n hwaddr offset)\n {\n@@ -212,6 +276,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n uint64_t value, unsigned size)\n {\n Tegra241CMDQV *cmdqv = (Tegra241CMDQV *)opaque;\n+ int index;\n \n if (offset >= TEGRA241_CMDQV_IO_LEN) {\n qemu_log_mask(LOG_UNIMP,\n@@ -238,6 +303,40 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset,\n case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3:\n tegra241_cmdqv_config_vintf_write(cmdqv, offset, value);\n break;\n+ case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN:\n+ /*\n+ * VINTF Page0 registers have the same per-VCMDQ layout as the\n+ * VCMDQ Page0 registers. Translate the VINTF aperture offset to the\n+ * equivalent VCMDQ aperture offset, then fall through to reuse the\n+ * common VCMDQ decoding logic below.\n+ */\n+ offset -= CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN:\n+ /*\n+ * Decode a per-VCMDQ register access.\n+ *\n+ * The hardware supports up to 128 identical VCMDQ instances; we\n+ * currently expose TEGRA241_CMDQV_MAX_CMDQ (= 2). Each VCMDQ\n+ * occupies a CMDQV_VCMDQ_STRIDE-byte window within the page.\n+ *\n+ * Extract the VCMDQ index and normalize to the VCMDQ0_* register\n+ * offset. A single helper services all instances via @index.\n+ */\n+ index = (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE;\n+ tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n+ index, value, size);\n+ break;\n+ case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */\n+ offset -= CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE;\n+ QEMU_FALLTHROUGH;\n+ case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H:\n+ /* Same decode logic as VCMDQ Page0 case above */\n+ index = (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE;\n+ tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STRIDE,\n+ index, value, size);\n+ break;\n default:\n qemu_log_mask(LOG_UNIMP, \"%s unhandled write access at 0x%\" PRIx64 \"\\n\",\n __func__, offset);\n", "prefixes": [ "v4", "16/31" ] }