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GET /api/1.2/patches/2223439/?format=api
{ "id": 2223439, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223439/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-7-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-7-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:27", "name": "[v4,06/31] hw/arm/smmuv3-accel: Introduce CMDQV ops interface", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0f92ebd0892b6f39e43dccfcc7bf3270fe504cfb", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-7-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223439/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=c969BvcM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c111::9;\n envelope-from=skolothumtho@nvidia.com;\n helo=DM5PR21CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 06/31] hw/arm/smmuv3-accel: Introduce CMDQV ops interface", "Date": "Wed, 15 Apr 2026 11:55:27 +0100", "Message-ID": "<20260415105552.622421-7-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3B:EE_|PH8PR12MB7159:EE_", "X-MS-Office365-Filtering-Correlation-Id": "21bfcf2f-22e5-480d-5010-08de9addc317", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|36860700016|82310400026|376014|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n 0TcicCWRcKWF0iaqSf6UfoAKzWU+Il9mrtn+3OIjDTFkQgzLNVrK1ETaoEbsFXnpaPP8nuGE3KthSdqk/hnrrES7Q2Szb7RbWD2jitIM0S6VqdkdqVEo6kDYSO4MWrLPu5KdPDZl7T2WFadOMExzK6ccDh/blE7LHRdWYejczFE4pr8EocHJ22zNs0yF2CUt4SG++Tq1AbTC1Q3G53EIp4OZXmdwat94cH6vaC5iobtQeicBCZlvrfcL6VRdj0b8Yr6TRr4c9ag8XcPRzR73Ahk5mZBjA3TEAkURdwenUJU+jKYSNLGsI4FXl4YoT51IF0rF87S+jznFmWntqxhHZuu8IuDPWLDHhNGiWDnJHrILa9Ht0pn+R6bnI6XcJPsFaze65jaRMf1MznUv5lqJZguXgVzSuE/j2z37wYZwQPnM+aVICFUhNPo6ojzYhtvZtY8im2NLm0HR5dtGsbdqa0Gf7nemlymUbSNlqwBLZWUmN1Ek/+CmQh0B4P6XROtFbQYiQxdWZ6wicoZ5pbjxzocA7DFUoqLB/qe+TmLn1+WCZIGP16fFr5pm4jAmVeawSKzGdZdpEGH21UL1ZMA18KqpIr1Cf82EG1jTqw35Pf1Y5I53mEctJfMKYmbhsDb67zI3WSswCwlgavjBgb6hUdKZkM1k7v4ylzbkmFzi48VBM9Gfby6DMsBC6HSmjuAMzKsAd0GDAOVWNUhnHXS5ERXuQu337Ur8TrNQ9hEui5NOnR+27Tx6p3DFnWN92nzbQbe+LYjom4r2j3N7MBVtdQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(56012099003)(22082099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n ewPaKXa79OvNlad/l2gu8IWpmC5vaRuVMKEihEy007r0t0QIUD2WccNFKzZJ4XnAqfBSZ4LQE84Hgo+10guJSiHJaxQuMV20Z1AhYTy5PLMJmF+Ydc2KBaUaw6QGbnCPli97mitAVMQUm4bdWhNEzaOefKnvhVMiMHrGohWHiI+5mloD5XN09PtPsr+6AzO1ihUki0OQnVnyF1e1hKC2Gdrv2iP9+gf9aLFyJnyDSQ94bFOPs+XoUukt5sR9XH4ZcSKRlajJi4B/qLZDribg9xkCrmMHgIjcQIxCG6fFtbPzmYEQkpkWTu8qvo9lOAVgwzUCQj1lOiFLJ0vkDHnIuWfDnnDYHRLZSY+lU50NJbzYpkkQf9gAA5Qf7tVvGLsv/94TDpe3Ds/8hKFnvOjo0VcZ3yQNkZezG/NbPZbQvZ4V9P9G0/WYxlBOHIiQ8tla", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:18.3389 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 21bfcf2f-22e5-480d-5010-08de9addc317", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3B.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7159", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Command Queue Virtualization (CMDQV) is a hardware extension available\non certain platforms that allows the SMMUv3 command queue to be\nvirtualized and passed through to a VM, improving performance.\n\nFor example, NVIDIA Tegra241 implements CMDQV to support virtualization\nof multiple command queues (VCMDQs).\n\nThe term CMDQV is used here generically to refer to any platform that\nprovides hardware support to virtualize the SMMUv3 command queue.\n\nCMDQV support is a specialization of the IOMMUFD-backed accelerated\nSMMUv3 path. Introduce an ops interface to factor out CMDQV-specific\nprobe, initialization, and vIOMMU allocation logic from the base\nimplementation. The ops pointer and associated state are stored in\nthe accelerated SMMUv3 state.\n\nThis provides an extensible design to support future vendor-specific\nCMDQV implementations.\n\nNo functional change.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex 7b4a0be000..86301afcb4 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -10,11 +10,28 @@\n #define HW_ARM_SMMUV3_ACCEL_H\n \n #include \"hw/arm/smmu-common.h\"\n+#include \"hw/arm/smmuv3.h\"\n #include \"system/iommufd.h\"\n #ifdef CONFIG_LINUX\n #include <linux/iommufd.h>\n #endif\n \n+/*\n+ * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to\n+ * support multiple VCMDQs with virtualization capabilities.\n+ * CMDQV specific behavior is factored behind this ops interface.\n+ */\n+typedef struct SMMUv3AccelCmdqvOps {\n+ bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **errp);\n+ bool (*init)(SMMUv3State *s, Error **errp);\n+ bool (*alloc_viommu)(SMMUv3State *s,\n+ HostIOMMUDeviceIOMMUFD *idev,\n+ uint32_t *out_viommu_id,\n+ Error **errp);\n+ void (*free_viommu)(SMMUv3State *s);\n+ void (*reset)(SMMUv3State *s);\n+} SMMUv3AccelCmdqvOps;\n+\n /*\n * Represents an accelerated SMMU instance backed by an iommufd vIOMMU object.\n * Holds bypass and abort proxy HWPT IDs used for device attachment.\n@@ -27,6 +44,7 @@ typedef struct SMMUv3AccelState {\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n bool auto_mode;\n bool auto_finalised;\n+ const SMMUv3AccelCmdqvOps *cmdqv_ops;\n } SMMUv3AccelState;\n \n typedef struct SMMUS1Hwpt {\n", "prefixes": [ "v4", "06/31" ] }