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GET /api/1.2/patches/2223438/?format=api
{ "id": 2223438, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223438/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-8-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-8-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:28", "name": "[v4,07/31] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f8f3d4d3b219d4fdb3a9fd88418b56a5ad249e11", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-8-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223438/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223438/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=pYihkkEd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c110::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=BN1PR04CU002.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 07/31] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops\n backend stub", "Date": "Wed, 15 Apr 2026 11:55:28 +0100", "Message-ID": "<20260415105552.622421-8-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F6C:EE_|SA1PR12MB9490:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c939b3cb-e095-4b92-a792-08de9addc1a9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n 7Wz69kVyBUVW38Rj0fWhoJksH8iOiRJbht0WRStaU/rIsC8+Rza4nNr3H93AV2Ur4X6RFT8eaJqSZFHYJWKqOl4j7eL3XmyjIbiqfKr0Nwxw1jIPA7GltNaK4fr7VCwyMd6VUepK48omBKgyNRKfNO5Dacav5s25NyujuHbsJ3mfn5sdmis29n3xENLzLSb3x99j/hJE7Xf5t0IHKNX/MaZXBDfwRdpSEBveu2ZyXqpEC6V5MdtmdjwgJTxW5Gdu9N9Y5rTbHFpLftQLoPysfKwk9PpeclIUqS0iNVU0RGr1AqsjRKP/uhhpTrArVHKRoa3ap7urZ1vy1QLgt+HdDv8eQhKetIkmNPKgxvLqWRlSZBbg8lHibtZVqJBnwF2FxARBZ66T/HoWWdAgmqVj8ptDGL+q1E6yPZmUDU1LWsceZZCA3yhuKze6lst/wex8eVqOUroi0myhxiLkSfXW0bdN/YAbqLrbXJv8zgFHhpMfoApQEqDeicckEp1lJm3tXADSXl6z3oEcC7QYA3KAdvynFTDGlSOjFhkk0bhmBcXoIFb8YFdntH5WquQVekbGl9e7e8sTO20Lio3M5+jCRHEH9Bb8fowBO3fiECgL8JoWj7pzQxNBc76eBYr/Nm+EgbizaIPPL0uPx7KDryoZ6+vOu4uoBAvpSXzID6325gFbmCR8Fkn3AhH3PUK2IPKpzeHIyXceryRa8rLOKFawpxcQg9uhASGJJAAojpJ4BO4whTWYeyRgc/yjQjnm71Ex8tvcZ/CpjyDHBRoKrDC9lQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(376014)(82310400026)(36860700016)(1800799024)(18002099003)(22082099003)(56012099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n mq1Pivn4KIrIWDBMSvGjATjFzIw5UyxVXmuBs6bA4tC3isPB4ilqyP2BOBtPqVxtxxRXqGLH29fUzjNw5aYFcKdgWYq/L2bZKm3q50AuIBgUsMvdOuKh11HGFbeVnmyqclcaxdPP3Dy1cZ53LXxrBfBdNxzy+jhjlUb0cWahSE26XGD0JPHvA1Lq3Jl50Qs1GJ7gB70JL2xGMurmxQRVRpoZkz3Au4kYrSlj15qqn6TrKARQOuoCynO+I1VnktANZV3DLFz19Hj31EfRE4ZC2LVl1eBZ6SwshTCF3xpNCpBFb8CtzIlhooc7UFUhWummSWqalOXZVoO0TzvtWhJOX4nPnFs3MKqbgSaP84LWDdohqw5OQmhjlYM7d+NSszutgP6EqDCdOIBdd/4QtO5Fjt/CjyKllPQOwd9LQpn2VWaCCwmlP/IQJdKWKsO6s6Vi", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:15.8848 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c939b3cb-e095-4b92-a792-08de9addc1a9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F6C.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB9490", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated\nCMDQV ops interface.\n\nThis patch wires up the Tegra241 CMDQV backend and provides a stub\nimplementation for CMDQV probe, initialization, vIOMMU allocation\nand reset handling.\n\nFunctional CMDQV support is added in follow-up patches.\n\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/tegra241-cmdqv.h | 15 ++++++++++\n hw/arm/tegra241-cmdqv-stubs.c | 16 ++++++++++\n hw/arm/tegra241-cmdqv.c | 56 +++++++++++++++++++++++++++++++++++\n hw/arm/Kconfig | 5 ++++\n hw/arm/meson.build | 2 ++\n 5 files changed, 94 insertions(+)\n create mode 100644 hw/arm/tegra241-cmdqv.h\n create mode 100644 hw/arm/tegra241-cmdqv-stubs.c\n create mode 100644 hw/arm/tegra241-cmdqv.c", "diff": "diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h\nnew file mode 100644\nindex 0000000000..07e10e86ee\n--- /dev/null\n+++ b/hw/arm/tegra241-cmdqv.h\n@@ -0,0 +1,15 @@\n+/*\n+ * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved\n+ * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3\n+ *\n+ * Written by Nicolin Chen, Shameer Kolothum\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_ARM_TEGRA241_CMDQV_H\n+#define HW_ARM_TEGRA241_CMDQV_H\n+\n+const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void);\n+\n+#endif /* HW_ARM_TEGRA241_CMDQV_H */\ndiff --git a/hw/arm/tegra241-cmdqv-stubs.c b/hw/arm/tegra241-cmdqv-stubs.c\nnew file mode 100644\nindex 0000000000..eabf90daf8\n--- /dev/null\n+++ b/hw/arm/tegra241-cmdqv-stubs.c\n@@ -0,0 +1,16 @@\n+/*\n+ * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved\n+ *\n+ * Stubs for Tegra241 CMDQ-Virtualiisation extension for SMMUv3\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"smmuv3-accel.h\"\n+#include \"hw/arm/tegra241-cmdqv.h\"\n+\n+const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void)\n+{\n+ return NULL;\n+}\ndiff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c\nnew file mode 100644\nindex 0000000000..ad5a0d4611\n--- /dev/null\n+++ b/hw/arm/tegra241-cmdqv.c\n@@ -0,0 +1,56 @@\n+/*\n+ * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved\n+ * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3\n+ *\n+ * Written by Nicolin Chen, Shameer Kolothum\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+\n+#include \"hw/arm/smmuv3.h\"\n+#include \"smmuv3-accel.h\"\n+#include \"tegra241-cmdqv.h\"\n+\n+static void tegra241_cmdqv_free_viommu(SMMUv3State *s)\n+{\n+}\n+\n+static bool\n+tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n+ uint32_t *out_viommu_id, Error **errp)\n+{\n+ error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n+ return false;\n+}\n+\n+static void tegra241_cmdqv_reset(SMMUv3State *s)\n+{\n+}\n+\n+static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp)\n+{\n+ error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n+ return false;\n+}\n+\n+static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n+ Error **errp)\n+{\n+ error_setg(errp, \"NVIDIA Tegra241 CMDQV is unsupported\");\n+ return false;\n+}\n+\n+static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops = {\n+ .probe = tegra241_cmdqv_probe,\n+ .init = tegra241_cmdqv_init,\n+ .alloc_viommu = tegra241_cmdqv_alloc_viommu,\n+ .free_viommu = tegra241_cmdqv_free_viommu,\n+ .reset = tegra241_cmdqv_reset,\n+};\n+\n+const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void)\n+{\n+ return &tegra241_cmdqv_ops;\n+}\ndiff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 4e50fb1111..073f2ebaaf 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -618,6 +618,10 @@ config FSL_IMX8MP_EVK\n depends on TCG\n select FSL_IMX8MP\n \n+config TEGRA241_CMDQV\n+ bool\n+ depends on ARM_SMMUV3_ACCEL\n+\n config ARM_SMMUV3_ACCEL\n bool\n depends on ARM_SMMUV3\n@@ -625,6 +629,7 @@ config ARM_SMMUV3_ACCEL\n config ARM_SMMUV3\n bool\n select ARM_SMMUV3_ACCEL if IOMMUFD\n+ imply TEGRA241_CMDQV\n \n config FSL_IMX6UL\n bool\ndiff --git a/hw/arm/meson.build b/hw/arm/meson.build\nindex 3be1252c4f..64bcdc5a7c 100644\n--- a/hw/arm/meson.build\n+++ b/hw/arm/meson.build\n@@ -87,6 +87,8 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c'))\n arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))\n arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c'))\n stub_ss.add(files('smmuv3-accel-stubs.c'))\n+arm_common_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-cmdqv.c'))\n+stub_ss.add(files('tegra241-cmdqv-stubs.c'))\n arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))\n arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))\n arm_common_ss.add(when: 'CONFIG_XEN', if_true: files(\n", "prefixes": [ "v4", "07/31" ] }