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GET /api/1.2/patches/2223437/?format=api
{ "id": 2223437, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2223437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-10-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-10-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:30", "name": "[v4,09/31] hw/arm/virt: Use stored SMMUv3 device list for IORT build", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "598edf76c69bd626527ed210a61c0bc2f660558d", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415105552.622421-10-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223437/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223437/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=QqztvOdp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c112::7;\n envelope-from=skolothumtho@nvidia.com;\n helo=CY3PR05CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 09/31] hw/arm/virt: Use stored SMMUv3 device list for IORT\n build", "Date": "Wed, 15 Apr 2026 11:55:30 +0100", "Message-ID": "<20260415105552.622421-10-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "References": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F69:EE_|SJ2PR12MB8783:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c901524c-dd05-4cf2-5c26-08de9addc73c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n TWxKDHbSnq7CZIweUqeqgFCAWClXxf7EJ9chtyIx+Kw86j1ruCUR27RQc98AG3uCl2sN79nmAoeDN1PgAtp0Y+FRwjaI01/03EA/hj41vuZk3wK8YH6ZkRRTjQqesyK22OKOXSY9Xy5jk0643T05/KbfajpuwkCDSff45wKWFY3TKUHoLIYb4+vQRU4bR2bvkSAh3bDMbm4z4Ya/zydG+1qAjEARP6R/QpodDSjTNgSrCGJPmCKgdGYeGSjlL4nuoXm8ABcSZEMKYcPoBUB0V/0A+os/DMZLkREYKBBSd+GsWbjhiaJgf7sj/JXOsYFe+ucOKW8YoBiStBWuITW9lGbtxUTZOA8xvHr1CQ1eYHQGiSY1kKuNaYmZHFxvHAyD6EC0K7D71oJIjEuzy5X3O3Z/1T+to+pUC7G+FGLG+ms3OawNWK+w5T8/1XKVhRJX/l0yJiAY5Lxz6tbayYeC9LuEQZcIeWVDc5/Wi/6CXfT7gEhhp7B4VBoDaeYprotl2gFYMjGhQg0abt2W/UupUaJX4WYgDePk18gRlI5n6yOot4SFhgZFM3TdXdPzWa0qrzk8Falrl0RE1jUidyhmRMbT55uZWuzk67w9es9Lt/Jl2RTPE5Wxa+lzGA/NZ+5zI+P19ciAvhIXYQeRcR1PI3hbmxyOIx2weiwqXyefuVeHYfrXdBTkHTDz35qZ1lCaikLDsXSj228erJRsCwionHnADd6s8mHj6CB4CZyD5LVrvy4pm7dWIQve5o1SH82JVS5PlG57QJScmcHt5voifA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(18002099003)(22082099003)(56012099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n PlxV99behzvQOquYhy24KZN5KuWQzZuj+RCTM1NbKOjr3nlCwNwS/uwgurzz9A2pd1CUD6J7cbu/UXNFy8f0XmPaytwAc8fayrdJjELk/rpVCsBQaF1LMPxrg/njzWES79Fc8s0IgEiucfmJXj7vjG02lBFmEt8Vfn42IA/pxix72SCuTi/90DArJnT/SizdA6OPWfv7YfGYEd7sz42BvijmAuDBaZJCSyg32Y9X9gdbzs4flEpOwSBnkgL9QAm/+DLGSyQl7KXH1/QAq/f44QvXBAUA/xfI1ESDfTeN31pU6J0zU3+ZSCnDntzLM1V6ANL6hGMaWhS7DtHueAL0oVu+eMmnkym3p7/ncb8NbyHH1fBMZXIaVzK+4yDYTpsFF+DJtDFJfWAhrxOo5rQodlegU4uAE46h/qs27snHorhFEEO3DWvCv2t5CKx9FfeO", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:25.2172 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c901524c-dd05-4cf2-5c26-08de9addc73c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF00021F69.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ2PR12MB8783", "X-Spam_score_int": "-15", "X-Spam_score": "-1.6", "X-Spam_bar": "-", "X-Spam_report": "(-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce a GPtrArray in VirtMachineState to track all SMMUv3 devices\ncreated on the virt machine, and use it when building the IORT table\ninstead of relying on object_child_foreach_recursive() walks of the\nobject tree.\n\nThis avoids recursive object traversal and provides a foundation for\nsubsequent patches that need direct access to SMMUv3 instances for\nCMDQV-related handling.\n\nNo functional change. No bios-tables qtest failures observed.\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n include/hw/arm/virt.h | 1 +\n hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++----------------------\n hw/arm/virt.c | 3 ++\n 3 files changed, 35 insertions(+), 39 deletions(-)", "diff": "diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex 5fcbd1c76f..a840a97de8 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -187,6 +187,7 @@ struct VirtMachineState {\n MemoryRegion *sysmem;\n MemoryRegion *secure_sysmem;\n bool pci_preserve_config;\n+ GPtrArray *smmuv3_devices;\n };\n \n #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 591cfc993c..521443de87 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -385,49 +385,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b)\n return map_a->input_base - map_b->input_base;\n }\n \n-static int iort_smmuv3_devices(Object *obj, void *opaque)\n-{\n- VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());\n- AcpiIortSMMUv3Dev sdev = {0};\n- GArray *sdev_blob = opaque;\n- AcpiIortIdMapping idmap;\n- PlatformBusDevice *pbus;\n- int min_bus, max_bus;\n- SysBusDevice *sbdev;\n- PCIBus *bus;\n-\n- if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) {\n- return 0;\n- }\n-\n- bus = PCI_BUS(object_property_get_link(obj, \"primary-bus\", &error_abort));\n- sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n- sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n- pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n- sbdev = SYS_BUS_DEVICE(obj);\n- sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\n- sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;\n- sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);\n- sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];\n- sdev.irq += ARM_SPI_BASE;\n-\n- pci_bus_range(bus, &min_bus, &max_bus);\n- sdev.rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));\n- idmap.input_base = min_bus << 8,\n- idmap.id_count = (max_bus - min_bus + 1) << 8,\n- g_array_append_val(sdev.rc_smmu_idmaps, idmap);\n- g_array_append_val(sdev_blob, sdev);\n- return 0;\n-}\n-\n /*\n * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and\n * return the total number of idmaps.\n */\n-static int populate_smmuv3_dev(GArray *sdev_blob)\n+static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob)\n {\n- object_child_foreach_recursive(object_get_root(),\n- iort_smmuv3_devices, sdev_blob);\n+ for (int i = 0; i < vms->smmuv3_devices->len; i++) {\n+ Object *obj = OBJECT(g_ptr_array_index(vms->smmuv3_devices, i));\n+ AcpiIortSMMUv3Dev sdev = {0};\n+ AcpiIortIdMapping idmap;\n+ PlatformBusDevice *pbus;\n+ int min_bus, max_bus;\n+ SysBusDevice *sbdev;\n+ PCIBus *bus;\n+\n+ bus = PCI_BUS(object_property_get_link(obj, \"primary-bus\",\n+ &error_abort));\n+ sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n+ sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n+ pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n+ sbdev = SYS_BUS_DEVICE(obj);\n+ sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\n+ sdev.base += vms->memmap[VIRT_PLATFORM_BUS].base;\n+ sdev.irq = platform_bus_get_irqn(pbus, sbdev, 0);\n+ sdev.irq += vms->irqmap[VIRT_PLATFORM_BUS];\n+ sdev.irq += ARM_SPI_BASE;\n+\n+ pci_bus_range(bus, &min_bus, &max_bus);\n+ sdev.rc_smmu_idmaps = g_array_new(false, true,\n+ sizeof(AcpiIortIdMapping));\n+ idmap.input_base = min_bus << 8;\n+ idmap.id_count = (max_bus - min_bus + 1) << 8;\n+ g_array_append_val(sdev.rc_smmu_idmaps, idmap);\n+ g_array_append_val(sdev_blob, sdev);\n+ }\n /* Sort the smmuv3 devices(if any) by smmu idmap input_base */\n g_array_sort(sdev_blob, smmuv3_dev_idmap_compare);\n /*\n@@ -561,7 +553,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)\n if (vms->legacy_smmuv3_present) {\n rc_smmu_idmaps_len = populate_smmuv3_legacy_dev(smmuv3_devs);\n } else {\n- rc_smmu_idmaps_len = populate_smmuv3_dev(smmuv3_devs);\n+ rc_smmu_idmaps_len = populate_smmuv3_dev(vms, smmuv3_devs);\n }\n \n num_smmus = smmuv3_devs->len;\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ec0d8475ca..68464ceb14 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -3261,6 +3261,7 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,\n }\n \n create_smmuv3_dev_dtb(vms, dev, bus, errp);\n+ g_ptr_array_add(vms->smmuv3_devices, dev);\n }\n }\n \n@@ -3697,6 +3698,8 @@ static void virt_instance_init(Object *obj)\n vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);\n vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);\n cxl_machine_init(obj, &vms->cxl_devices_state);\n+\n+ vms->smmuv3_devices = g_ptr_array_new_with_free_func(NULL);\n }\n \n static const TypeInfo virt_machine_info = {\n", "prefixes": [ "v4", "09/31" ] }