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GET /api/1.2/patches/2222475/?format=api
{ "id": 2222475, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2222475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/51360220ee90a76ca326a4205f1f62b34a4a8624.1775959096.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<51360220ee90a76ca326a4205f1f62b34a4a8624.1775959096.git.chao.liu.zevorn@gmail.com>", "list_archive_url": null, "date": "2026-04-12T02:20:19", "name": "[v6,2/7] target/riscv: add sdext debug CSRs state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "aedb8f6e288248278e8da1b07c29cc01e55f5723", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/1.2/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/51360220ee90a76ca326a4205f1f62b34a4a8624.1775959096.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 499584, "url": "http://patchwork.ozlabs.org/api/1.2/series/499584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584", "date": "2026-04-12T02:20:20", "name": "riscv: add initial sdext support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222475/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ja5wGNqP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf43.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nAdd architectural state for Sdext Debug Mode: debug_mode, dcsr, dpc\nand dscratch0/1. Wire up CSR access for dcsr/dpc/dscratch and gate\nthem to Debug Mode (or host debugger access).\n\nThe Sdext is not fully implemented, so it is disabled by default.\n\nSigned-off-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nTested-by: Tao Tang <tangtao1634@phytium.com.cn>\n---\n target/riscv/cpu.c | 8 ++\n target/riscv/cpu.h | 4 +\n target/riscv/cpu_bits.h | 33 ++++++++\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n target/riscv/csr.c | 126 ++++++++++++++++++++++++++++++\n target/riscv/machine.c | 20 +++++\n 6 files changed, 192 insertions(+)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 6208201538..de9ba8dfb0 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -210,6 +210,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),\n ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),\n ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),\n+ ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext),\n ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),\n ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),\n ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),\n@@ -783,6 +784,12 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)\n env->vill = true;\n \n #ifndef CONFIG_USER_ONLY\n+ env->debug_mode = false;\n+ env->dcsr = DCSR_DEBUGVER(4);\n+ env->dpc = 0;\n+ env->dscratch[0] = 0;\n+ env->dscratch[1] = 0;\n+\n if (cpu->cfg.ext_sdtrig) {\n riscv_trigger_reset_hold(env);\n }\n@@ -1248,6 +1255,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {\n MULTI_EXT_CFG_BOOL(\"smcdeleg\", ext_smcdeleg, false),\n MULTI_EXT_CFG_BOOL(\"sscsrind\", ext_sscsrind, false),\n MULTI_EXT_CFG_BOOL(\"ssccfg\", ext_ssccfg, false),\n+ MULTI_EXT_CFG_BOOL(\"sdext\", ext_sdext, false),\n MULTI_EXT_CFG_BOOL(\"sdtrig\", ext_sdtrig, true),\n MULTI_EXT_CFG_BOOL(\"smctr\", ext_smctr, false),\n MULTI_EXT_CFG_BOOL(\"ssctr\", ext_ssctr, false),\ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53..2a265faae5 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -476,6 +476,10 @@ struct CPUArchState {\n \n /* True if in debugger mode. */\n bool debugger;\n+ bool debug_mode;\n+ target_ulong dcsr;\n+ target_ulong dpc;\n+ target_ulong dscratch[2];\n \n uint64_t mstateen[SMSTATEEN_MAX_COUNT];\n uint64_t hstateen[SMSTATEEN_MAX_COUNT];\ndiff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\nindex b62dd82fe7..bb59f7ff56 100644\n--- a/target/riscv/cpu_bits.h\n+++ b/target/riscv/cpu_bits.h\n@@ -467,6 +467,39 @@\n #define CSR_DCSR 0x7b0\n #define CSR_DPC 0x7b1\n #define CSR_DSCRATCH 0x7b2\n+#define CSR_DSCRATCH1 0x7b3\n+\n+/* DCSR fields */\n+#define DCSR_XDEBUGVER_SHIFT 28\n+#define DCSR_XDEBUGVER_MASK (0xfu << DCSR_XDEBUGVER_SHIFT)\n+#define DCSR_DEBUGVER(val) ((target_ulong)(val) << DCSR_XDEBUGVER_SHIFT)\n+#define DCSR_EXTCAUSE_SHIFT 24\n+#define DCSR_EXTCAUSE_MASK (0x7u << DCSR_EXTCAUSE_SHIFT)\n+#define DCSR_CETRIG BIT(19)\n+#define DCSR_PELP BIT(18)\n+#define DCSR_EBREAKVS BIT(17)\n+#define DCSR_EBREAKVU BIT(16)\n+#define DCSR_EBREAKM BIT(15)\n+#define DCSR_EBREAKS BIT(13)\n+#define DCSR_EBREAKU BIT(12)\n+#define DCSR_STEPIE BIT(11)\n+#define DCSR_STOPCOUNT BIT(10)\n+#define DCSR_STOPTIME BIT(9)\n+#define DCSR_CAUSE_SHIFT 6\n+#define DCSR_CAUSE_MASK (0x7u << DCSR_CAUSE_SHIFT)\n+#define DCSR_V BIT(5)\n+#define DCSR_MPRVEN BIT(4)\n+#define DCSR_NMIP BIT(3)\n+#define DCSR_STEP BIT(2)\n+#define DCSR_PRV_MASK 0x3u\n+\n+#define DCSR_CAUSE_EBREAK 1\n+#define DCSR_CAUSE_TRIGGER 2\n+#define DCSR_CAUSE_HALTREQ 3\n+#define DCSR_CAUSE_STEP 4\n+#define DCSR_CAUSE_RESET 5\n+#define DCSR_CAUSE_GROUP 6\n+#define DCSR_CAUSE_OTHER 7\n \n /* Performance Counters */\n #define CSR_MHPMCOUNTER3 0xb03\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 44235bfaa1..3d2de307a2 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -46,6 +46,7 @@ BOOL_FIELD(ext_zilsd)\n BOOL_FIELD(ext_zimop)\n BOOL_FIELD(ext_zcmop)\n BOOL_FIELD(ext_ztso)\n+BOOL_FIELD(ext_sdext)\n BOOL_FIELD(ext_sdtrig)\n BOOL_FIELD(ext_smstateen)\n BOOL_FIELD(ext_sstc)\ndiff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 93b4864933..e8dc2d9e8a 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -3147,6 +3147,126 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,\n return RISCV_EXCP_NONE;\n }\n \n+#if !defined(CONFIG_USER_ONLY)\n+static RISCVException sdext(CPURISCVState *env, int csrno)\n+{\n+ if (!riscv_cpu_cfg(env)->ext_sdext) {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+\n+ if (!env->debug_mode && !env->debugger) {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static target_ulong dcsr_visible_mask(CPURISCVState *env)\n+{\n+ target_ulong mask = (target_ulong)-1;\n+ RISCVCPU *cpu = env_archcpu(env);\n+\n+ if (!riscv_has_ext(env, RVH)) {\n+ mask &= ~(DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V);\n+ }\n+ if (!riscv_has_ext(env, RVS)) {\n+ mask &= ~DCSR_EBREAKS;\n+ }\n+ if (!riscv_has_ext(env, RVU)) {\n+ mask &= ~DCSR_EBREAKU;\n+ }\n+ if (!cpu->cfg.ext_zicfilp) {\n+ mask &= ~DCSR_PELP;\n+ }\n+ if (!cpu->cfg.ext_smdbltrp) {\n+ mask &= ~DCSR_CETRIG;\n+ }\n+\n+ return mask;\n+}\n+\n+static RISCVException read_dcsr(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ *val = env->dcsr & dcsr_visible_mask(env);\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static target_ulong dcsr_writable_mask(CPURISCVState *env)\n+{\n+ target_ulong mask = DCSR_EBREAKM | DCSR_EBREAKS | DCSR_EBREAKU |\n+ DCSR_STEPIE | DCSR_STOPCOUNT | DCSR_STOPTIME |\n+ DCSR_STEP | DCSR_PRV_MASK;\n+ RISCVCPU *cpu = env_archcpu(env);\n+\n+ mask |= DCSR_MPRVEN;\n+\n+ if (riscv_has_ext(env, RVH)) {\n+ mask |= DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V;\n+ }\n+ if (riscv_has_ext(env, RVS)) {\n+ mask |= DCSR_EBREAKS;\n+ }\n+ if (riscv_has_ext(env, RVU)) {\n+ mask |= DCSR_EBREAKU;\n+ }\n+ if (cpu->cfg.ext_zicfilp) {\n+ mask |= DCSR_PELP;\n+ }\n+ if (cpu->cfg.ext_smdbltrp) {\n+ mask |= DCSR_CETRIG;\n+ }\n+\n+ return mask;\n+}\n+\n+static RISCVException write_dcsr(CPURISCVState *env, int csrno,\n+ target_ulong val, uintptr_t ra)\n+{\n+ target_ulong mask = dcsr_writable_mask(env);\n+ target_ulong new_val = env->dcsr;\n+\n+ new_val &= ~mask;\n+ new_val |= val & mask;\n+ new_val &= ~DCSR_XDEBUGVER_MASK;\n+ new_val |= DCSR_DEBUGVER(4);\n+ env->dcsr = new_val;\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException read_dpc(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ *val = env->dpc & get_xepc_mask(env);\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException write_dpc(CPURISCVState *env, int csrno,\n+ target_ulong val, uintptr_t ra)\n+{\n+ env->dpc = val & get_xepc_mask(env);\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException read_dscratch(CPURISCVState *env, int csrno,\n+ target_ulong *val)\n+{\n+ int index = (csrno == CSR_DSCRATCH1) ? 1 : 0;\n+\n+ *val = env->dscratch[index];\n+ return RISCV_EXCP_NONE;\n+}\n+\n+static RISCVException write_dscratch(CPURISCVState *env, int csrno,\n+ target_ulong val, uintptr_t ra)\n+{\n+ int index = (csrno == CSR_DSCRATCH1) ? 1 : 0;\n+\n+ env->dscratch[index] = val;\n+ return RISCV_EXCP_NONE;\n+}\n+#endif /* !CONFIG_USER_ONLY */\n+\n /* Execution environment configuration setup */\n static RISCVException read_menvcfg(CPURISCVState *env, int csrno,\n target_ulong *val)\n@@ -6316,6 +6436,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {\n [CSR_TDATA3] = { \"tdata3\", debug, read_tdata, write_tdata },\n [CSR_TINFO] = { \"tinfo\", debug, read_tinfo, write_ignore },\n [CSR_MCONTEXT] = { \"mcontext\", debug, read_mcontext, write_mcontext },\n+#if !defined(CONFIG_USER_ONLY)\n+ [CSR_DCSR] = { \"dcsr\", sdext, read_dcsr, write_dcsr },\n+ [CSR_DPC] = { \"dpc\", sdext, read_dpc, write_dpc },\n+ [CSR_DSCRATCH] = { \"dscratch0\", sdext, read_dscratch, write_dscratch },\n+ [CSR_DSCRATCH1] = { \"dscratch1\", sdext, read_dscratch, write_dscratch },\n+#endif\n \n [CSR_MCTRCTL] = { \"mctrctl\", ctr_mmode, NULL, NULL, rmw_xctrctl },\n [CSR_SCTRCTL] = { \"sctrctl\", ctr_smode, NULL, NULL, rmw_xctrctl },\ndiff --git a/target/riscv/machine.c b/target/riscv/machine.c\nindex 62c51c8033..52264cf047 100644\n--- a/target/riscv/machine.c\n+++ b/target/riscv/machine.c\n@@ -248,6 +248,25 @@ static const VMStateDescription vmstate_sdtrig = {\n VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),\n VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),\n VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),\n+ VMSTATE_BOOL_V(env.debug_mode, RISCVCPU, 3),\n+ VMSTATE_UINTTL_V(env.dcsr, RISCVCPU, 3),\n+ VMSTATE_UINTTL_V(env.dpc, RISCVCPU, 3),\n+ VMSTATE_UINTTL_ARRAY_V(env.dscratch, RISCVCPU, 2, 3),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static const VMStateDescription vmstate_sdext = {\n+ .name = \"cpu/sdext\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = sdtrig_needed,\n+ .post_load = sdtrig_post_load,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_BOOL_V(env.debug_mode, RISCVCPU, 3),\n+ VMSTATE_UINTTL_V(env.dcsr, RISCVCPU, 3),\n+ VMSTATE_UINTTL_V(env.dpc, RISCVCPU, 3),\n+ VMSTATE_UINTTL_ARRAY_V(env.dscratch, RISCVCPU, 2, 3),\n VMSTATE_END_OF_LIST()\n }\n };\n@@ -499,6 +518,7 @@ const VMStateDescription vmstate_riscv_cpu = {\n &vmstate_ctr,\n &vmstate_sstc,\n &vmstate_sdtrig,\n+ &vmstate_sdext,\n NULL\n }\n };\n", "prefixes": [ "v6", "2/7" ] }