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GET /api/1.2/patches/2222397/?format=api
{ "id": 2222397, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2222397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260411-waveshare-dsi-touch-v2-7-75cdbeac5156@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260411-waveshare-dsi-touch-v2-7-75cdbeac5156@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-11T12:10:27", "name": "[v2,07/21] drm/panel: himax-hx83102: support Waveshare 12.3\" DSI panel", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "734071b6a247642195aac5226ef72ca0b3579de2", "submitter": { "id": 90483, "url": "http://patchwork.ozlabs.org/api/1.2/people/90483/?format=api", "name": "Dmitry Baryshkov", "email": "dmitry.baryshkov@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260411-waveshare-dsi-touch-v2-7-75cdbeac5156@oss.qualcomm.com/mbox/", "series": [ { "id": 499552, "url": "http://patchwork.ozlabs.org/api/1.2/series/499552/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499552", "date": "2026-04-11T12:10:21", "name": "drm/panel: support Waveshare DSI TOUCH kits", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499552/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222397/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222397/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35036-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=PQd9pc7d;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Ucj/2+Xz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260411-waveshare-dsi-touch-v2-7-75cdbeac5156@oss.qualcomm.com>", "References": "<20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>", "In-Reply-To": "<20260411-waveshare-dsi-touch-v2-0-75cdbeac5156@oss.qualcomm.com>", "To": "Neil Armstrong <neil.armstrong@linaro.org>,\n Jessica Zhang <jesszhan0024@gmail.com>,\n David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n Maxime Ripard <mripard@kernel.org>,\n Thomas Zimmermann <tzimmermann@suse.de>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Cong Yang <yangcong5@huaqin.corp-partner.google.com>,\n Ondrej Jirman <megi@xff.cz>,\n Javier Martinez Canillas <javierm@redhat.com>,\n Jagan Teki <jagan@edgeble.ai>, Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Bartosz Golaszewski <brgl@kernel.org>", "Cc": "dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=8981;\n i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id;\n bh=i3q+ZnanPV6G/1cXFp+xLd7TApeXEUOIHGf51LyJVuc=;\n b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBp2jpF8uTwcBObArCbTTBldsTi3CrIuMFueegoj\n HVb00f0jymJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCado6RQAKCRCLPIo+Aiko\n 1Yn2B/950ZvwLklYqtNN0LZoJzkZQylRolF2pPKy2ExV1h102ubKyQYlApY1jO9xv0uz37QjpM+\n Sj0t1MJAlDUul79GmiNiVUD7fiLaOurr+vKqCJridTBLn7WirF2dLEqeeBiTzq7KVD9da34o7fG\n bbJpV6+j72KD1KAb/0mopkr42VmnzpXHSKQERCC4bm7TujRk4XmoyWgguFMMf6Z8A1kN7cKVl0j\n DJJoFjLw5ri8PSjv/n8zgiyNg61r9PobntlJHtdzDqT9KwlfE6Poa6yfY1WmBjsIqpb95C7NKAU\n Ywod4d01f7C9Pw1UtHpd7RjdPXeN3t7tNzATx07Hm2DSE2nu", "X-Developer-Key": "i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp;\n fpr=8F88381DD5C873E4AE487DA5199BF1243632046A", "X-Authority-Analysis": "v=2.4 cv=bcFbluPB c=1 sm=1 tr=0 ts=69da3a58 cx=c_pps\n a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8\n a=6dGl3bZOZdHCWiLLNVsA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDExMDEwMiBTYWx0ZWRfX57xLwt40uhvi\n rAiC1YDuwaFkviq/Xs5WnmJ+qnEfOngm5hDguWwnpQ8LqYTAAk7M8zkUJjaoI5ABgRC6OFxiUfF\n bCWxN+dWPL2CiDHD2Xq3M8wxUemaHp2QLZ21wuhhZNZPtFVAimobkzkJ+YWCNhj2LFL9az2Abeu\n RBJ++b1S/vHTt6TSLu68DQbM3PihqLy6h5pkwihirz8/O3UsTjtqd4+MRIuEUNJbdquvB5mxCil\n Ffc9Nza2UHzqqrIcQfFYz6lavSUqvTRcc//UghfnG0kQPq/ddvibdy9YfN9dZ1M8+uzWe6bYWmI\n gA/G3it7bcnpz0DDjSi3KF4dZano2H9gErIpY3TpEzATX6GITaPK9k2DYtwcWQyqpuclqtuggp9\n b6Xld9/OFgZQtX8gH3hvCjw75cG9dTn36kKG7C0I1X9gODh8vmB7C8G0hWy/Wn9CWRxpkodtzDh\n adnQa4YPZvVgVQ+9Yzw==", "X-Proofpoint-ORIG-GUID": "3YrYxFapFylWfG1pgxHP7aqqTj46Axei", "X-Proofpoint-GUID": "3YrYxFapFylWfG1pgxHP7aqqTj46Axei", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-11_03,2026-04-09_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0\n suspectscore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604110102" }, "content": "Add support for the Waveshare 12.3\" DSI TOUCH-A panel. According to the\nvendor driver, it uses different mode_flags, so let the panel\ndescriptions override driver-wide defaults.\n\nSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>\n---\n drivers/gpu/drm/panel/panel-himax-hx83102.c | 144 +++++++++++++++++++++++++++-\n 1 file changed, 142 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c\nindex 8b2a68ee851e..eab67893da86 100644\n--- a/drivers/gpu/drm/panel/panel-himax-hx83102.c\n+++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c\n@@ -29,11 +29,14 @@\n #define HX83102_UNKNOWN_B8\t0xb8\n #define HX83102_SETEXTC\t\t0xb9\n #define HX83102_SETMIPI\t\t0xba\n+#define HX83102_UNKNOWN_BB\t0xbb\n #define HX83102_SETVDC\t\t0xbc\n #define HX83102_SETBANK\t\t0xbd\n #define HX83102_UNKNOWN_BE\t0xbe\n #define HX83102_SETPTBA\t\t0xbf\n #define HX83102_SETSTBA\t\t0xc0\n+#define HX83102_UNKNOWN_C2\t0xc2\n+#define HX83102_UNKNOWN_C6\t0xc6\n #define HX83102_SETTCON\t\t0xc7\n #define HX83102_SETRAMDMY\t0xc8\n #define HX83102_SETPWM\t\t0xc9\n@@ -78,6 +81,7 @@ struct hx83102_panel_desc {\n \t} size;\n \n \tbool has_backlight;\n+\tunsigned long mode_flags;\n \n \tint (*init)(struct hx83102 *ctx);\n };\n@@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)\n \treturn dsi_ctx.accum_err;\n }\n \n+/* This is HX83102-E, assuming commands are the same as the normal HX83102 */\n+static int waveshare_12_3_a_init(struct hx83102 *ctx)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,\n+\t\t\t\t 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,\n+\t\t\t\t 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,\n+\t\t\t\t 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,\n+\t\t\t\t 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,\n+\t\t\t\t 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,\n+\t\t\t\t 0x01, 0x58, 0x00, 0xff, 0x00, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n+\t\t\t\t 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,\n+\t\t\t\t 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,\n+\t\t\t\t 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,\n+\t\t\t\t 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,\n+\t\t\t\t 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,\n+\t\t\t\t 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,\n+\t\t\t\t 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,\n+\t\t\t\t 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,\n+\t\t\t\t 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,\n+\t\t\t\t 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,\n+\t\t\t\t 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,\n+\t\t\t\t 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,\n+\t\t\t\t 0x01);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,\n+\t\t\t\t 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,\n+\t\t\t\t 0x08, 0x00, 0x63, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,\n+\t\t\t\t 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,\n+\t\t\t\t 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,\n+\t\t\t\t 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,\n+\t\t\t\t 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,\n+\t\t\t\t 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,\n+\t\t\t\t 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,\n+\t\t\t\t 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,\n+\t\t\t\t 0x98, 0x98, 0x98, 0x98);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,\n+\t\t\t\t 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,\n+\t\t\t\t 0x2a, 0xaa, 0xaa, 0xaa);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,\n+\t\t\t\t 0xaa, 0xaa);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,\n+\t\t\t\t 0xff, 0xff, 0xff, 0xff,\n+\t\t\t\t 0xff, 0xf0, 0xff, 0xff,\n+\t\t\t\t 0xff, 0xff, 0xff, 0xf0);\n+\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);\n+\n+\treturn dsi_ctx.accum_err;\n+};\n+\n static const struct drm_display_mode starry_mode = {\n \t.clock = 162680,\n \t.hdisplay = 1200,\n@@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {\n \t.init = holitech_htf065h045_init,\n };\n \n+static const struct drm_display_mode waveshare_12_3_a_mode = {\n+\t.clock = 95000,\n+\t.hdisplay = 720,\n+\t.hsync_start = 720 + 10,\n+\t.hsync_end = 720 + 10 + 10,\n+\t.htotal = 720 + 10 + 10 + 12,\n+\t.vdisplay = 1920,\n+\t.vsync_start = 1920 + 64,\n+\t.vsync_end = 1920 + 64 + 18,\n+\t.vtotal = 1920 + 64 + 18 + 4,\n+\t.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {\n+\t.modes = &waveshare_12_3_a_mode,\n+\t.size = {\n+\t\t.width_mm = 109,\n+\t\t.height_mm = 292,\n+\t},\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+\t.init = waveshare_12_3_a_init,\n+};\n+\n static int hx83102_enable(struct drm_panel *panel)\n {\n \tmsleep(130);\n@@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)\n \tdesc = of_device_get_match_data(&dsi->dev);\n \tdsi->lanes = 4;\n \tdsi->format = MIPI_DSI_FMT_RGB888;\n-\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n-\t\t\t\t\t MIPI_DSI_MODE_LPM;\n+\tif (desc->mode_flags)\n+\t\tdsi->mode_flags = desc->mode_flags;\n+\telse\n+\t\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO |\n+\t\t\tMIPI_DSI_MODE_VIDEO_SYNC_PULSE |\n+\t\t\tMIPI_DSI_MODE_LPM;\n \tctx->desc = desc;\n \tctx->dsi = dsi;\n \tret = hx83102_panel_add(ctx);\n@@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {\n \t{ .compatible = \"holitech,htf065h045\",\n \t .data = &holitech_htf065h045_desc\n \t},\n+\t{ .compatible = \"waveshare,12.3-dsi-touch-a\",\n+\t .data = &waveshare_12_3_inch_a_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, hx83102_of_match);\n", "prefixes": [ "v2", "07/21" ] }