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GET /api/1.2/patches/2222308/?format=api
{ "id": 2222308, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2222308/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260411-qcom_spl-v2-4-9609557cf562@seznam.cz/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260411-qcom_spl-v2-4-9609557cf562@seznam.cz>", "list_archive_url": null, "date": "2026-04-11T00:00:09", "name": "[v2,04/10] mach-snapdragon: boot0.h: split out msm8916_boot0.h", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c54d6241bf77c6dea1d5e18eef0379e69f248155", "submitter": { "id": 77645, "url": "http://patchwork.ozlabs.org/api/1.2/people/77645/?format=api", "name": "Michael Srba", "email": "michael.srba@seznam.cz" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260411-qcom_spl-v2-4-9609557cf562@seznam.cz/mbox/", "series": [ { "id": 499535, "url": "http://patchwork.ozlabs.org/api/1.2/series/499535/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499535", "date": "2026-04-11T00:00:12", "name": "Add SPL support for Qualcomm platforms, starting with sdm845", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499535/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222308/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222308/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=seznam.cz header.i=@seznam.cz header.a=rsa-sha256\n header.s=szn1 header.b=SB/P/foS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Sat, 11 Apr 2026 02:04:14 +0200 (CEST)", "from mxd-1-a04.seznam.cz (mxd-1-a04.seznam.cz\n [IPv6:2a02:598:128:8a00::1000:a04])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6993D83DC9\n for <u-boot@lists.denx.de>; Sat, 11 Apr 2026 02:04:01 +0200 (CEST)", "from email.seznam.cz by smtpc-mxd-7644845457-4tx79\n (smtpc-mxd-7644845457-4tx79 [2a02:598:128:8a00::1000:a04])\n id 2e971061759944082f3edc3f; Sat, 11 Apr 2026 02:03:20 +0200 (CEST)", "from [127.0.0.1] (ip-111-27.static.ccinternet.cz [147.161.27.111])\n by smtpd-relay-6597cc8696-xddnz (szn-email-smtpd/2.0.72) with ESMTPA\n id a2bb4aca-f80b-47f8-b3b9-d1189f5e1b34;\n Sat, 11 Apr 2026 02:03:01 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=seznam.cz; s=szn1;\n t=1775865800; bh=X9d10I4leoqIuE8hido0XqcxyGyUXPTxNKDzTftwSIw=;\n h=From:Date:Subject:MIME-Version:Content-Type:\n Content-Transfer-Encoding:Message-Id:To:Cc;\n b=SB/P/foSU/SsLjGlQeFzw0QTZiHOYjHnwshD3gt8JNc8Jc+e4MsF/t1lu6rlq6jSe\n EucvTqTETQTBvf9hQ/H4wgk1Kbb5h9WuSiJR+soeGxwH5vViYfqBcD9esEdtykLwjN\n c/Ge76wAdsr6lD/jeocLmN+RJmTuSXtJxYouEllQXzXAp7fswUWyB/1SEkkUqzNDI5\n plPBMsd7qyPMpLP5Zx7Ux+Rn3dITDaKkiZ0PkQaGTfdGhyZdVcZY8On0KQvqp0zop8\n 1/55ndb70QI4vcq7vjnjdnEdnRVYYPTmEB8cZqQH3quTji0BF7SssaQReAXqj+ZZKE\n bgUoKLHsc+Mrw==", "From": "michael.srba@seznam.cz", "Date": "Sat, 11 Apr 2026 02:00:09 +0200", "Subject": "[PATCH v2 04/10] mach-snapdragon: boot0.h: split out msm8916_boot0.h", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260411-qcom_spl-v2-4-9609557cf562@seznam.cz>", "References": "<20260411-qcom_spl-v2-0-9609557cf562@seznam.cz>", "In-Reply-To": "<20260411-qcom_spl-v2-0-9609557cf562@seznam.cz>", "To": "u-boot@lists.denx.de, Sumit Garg <sumit.garg@kernel.org>,\n u-boot-qcom@groups.io", "Cc": "Tom Rini <trini@konsulko.com>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Simon Glass <sjg@chromium.org>, Sughosh Ganu <sughosh.ganu@arm.com>,\n Anshul Dalal <anshuld@ti.com>, Peng Fan <peng.fan@nxp.com>,\n Mattijs Korpershoek <mkorpershoek@kernel.org>,\n Quentin Schulz <quentin.schulz@cherry.de>,\n Heinrich Schuchardt <xypron.glpk@gmx.de>, Andrew Davis <afd@ti.com>,\n Hrushikesh Salunke <h-salunke@ti.com>,\n Dario Binacchi <dario.binacchi@amarulasolutions.com>, Ye Li <ye.li@nxp.com>,\n Andre Przywara <andre.przywara@arm.com>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,\n Leo Yu-Chi Liang <ycliang@andestech.com>,\n Andrew Goodbody <andrew.goodbody@linaro.org>, Dhruva Gole <d-gole@ti.com>,\n Kaustabh Chakraborty <kauschluss@disroot.org>,\n Jerome Forissier <jerome.forissier@arm.com>,\n Heiko Schocher <hs@nabladev.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Lukasz Majewski <lukma@denx.de>,\n Mateusz Kulikowski <mateusz.kulikowski@gmail.com>,\n Dinesh Maniyam <dinesh.maniyam@altera.com>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Patrick Delaunay <patrick.delaunay@foss.st.com>,\n Michal Simek <michal.simek@amd.com>, Yao Zi <me@ziyao.cc>,\n Peter Korsgaard <peter@korsgaard.com>,\n Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>,\n Casey Connolly <casey.connolly@linaro.org>,\n Tingting Meng <tingting.meng@altera.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>, Alice Guo <alice.guo@nxp.com>,\n George Chan <gchan9527@gmail.com>,\n Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>,\n Alexey Charkov <alchark@gmail.com>, Ronald Wahl <ronald.wahl@legrand.com>,\n Michael Srba <Michael.Srba@seznam.cz>", "X-Mailer": "b4 0.15.1", "X-Mailman-Approved-At": "Sat, 11 Apr 2026 09:08:55 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Michael Srba <Michael.Srba@seznam.cz>\n\nPrepare for supporting alternative boot0.h per-SoC by splitting out\nthe existing msm8916-specific code.\n\nSigned-off-by: Michael Srba <Michael.Srba@seznam.cz>\n---\n arch/arm/mach-snapdragon/include/mach/boot0.h | 57 ++--------------------\n .../mach-snapdragon/include/mach/msm8916_boot0.h | 54 ++++++++++++++++++++\n 2 files changed, 59 insertions(+), 52 deletions(-)", "diff": "diff --git a/arch/arm/mach-snapdragon/include/mach/boot0.h b/arch/arm/mach-snapdragon/include/mach/boot0.h\nindex 953cccad790..44a764788de 100644\n--- a/arch/arm/mach-snapdragon/include/mach/boot0.h\n+++ b/arch/arm/mach-snapdragon/include/mach/boot0.h\n@@ -1,54 +1,7 @@\n /* SPDX-License-Identifier: GPL-2.0+ */\n-/*\n- * Workaround for \"PSCI bug\" on DragonBoard 410c\n- * Copyright (C) 2021 Stephan Gerhold <stephan@gerhold.net>\n- *\n- * Syscall parameters taken from Qualcomm's LK fork (scm.h):\n- * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.\n- *\n- * The PSCI implementation in the TrustZone/tz firmware on DragonBoard 410c has\n- * a bug that starts all other CPU cores in 32-bit mode unless the TZ syscall\n- * that switches from 32-bit to 64-bit mode is executed at least once.\n- *\n- * Normally this happens inside Qualcomm's LK bootloader which runs in 32-bit\n- * mode and uses the TZ syscall to boot a kernel in 64-bit mode. However, if\n- * U-Boot is installed to the \"aboot\" partition (replacing LK) the switch to\n- * 64-bit mode never happens since U-Boot is already running in 64-bit mode.\n- *\n- * A workaround for this \"PSCI bug\" is to execute the TZ syscall when entering\n- * U-Boot. That way PSCI is made aware of the 64-bit switch and starts all other\n- * CPU cores in 64-bit mode as well.\n- */\n-#include <linux/arm-smccc.h>\n-\n-#define ARM_SMCCC_SIP32_FAST_CALL \\\n-\tARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, ARM_SMCCC_OWNER_SIP, 0)\n-\n-\t/*\n-\t * U-Boot might be started in EL2 or EL3 with custom firmware.\n-\t * In that case, we assume that the workaround is not necessary or is\n-\t * handled already by the alternative firmware. Using the syscall in EL2\n-\t * would demote U-Boot to EL1; in EL3 it would probably just crash.\n-\t */\n-\tmrs\tx0, CurrentEL\n-\tcmp\tx0, #(1 << 2)\t/* EL1 */\n-\tbne\treset\n-\n-\t/* Prepare TZ syscall parameters */\n-\tmov\tx0, #ARM_SMCCC_SIP32_FAST_CALL\n-\tmovk\tx0, #0x10f\t/* SCM_SVC_MILESTONE_CMD_ID */\n-\tmov\tx1, #0x12\t/* MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ) */\n-\tadr\tx2, el1_system_param\n-\tmov\tx3, el1_system_param_end - el1_system_param\n-\n-\t/* Switch PSCI to 64-bit mode. Resets CPU and returns at el1_elr */\n-\tsmc\t#0\n-\n-\t/* Something went wrong, perhaps PSCI is already in 64-bit mode? */\n+#if defined(CONFIG_SPL_BUILD)\n \tb\treset\n-\n-\t.align\t3\n-el1_system_param:\n-\t.quad\t0, 0, 0, 0, 0, 0, 0, 0, 0\t/* el1_x0-x8 */\n-\t.quad\treset\t\t\t\t/* el1_elr */\n-el1_system_param_end:\n+#else\n+/* currently only db410c enables boot0.h in u-boot proper */\n+#include \"msm8916_boot0.h\"\n+#endif\ndiff --git a/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h b/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h\nnew file mode 100644\nindex 00000000000..953cccad790\n--- /dev/null\n+++ b/arch/arm/mach-snapdragon/include/mach/msm8916_boot0.h\n@@ -0,0 +1,54 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Workaround for \"PSCI bug\" on DragonBoard 410c\n+ * Copyright (C) 2021 Stephan Gerhold <stephan@gerhold.net>\n+ *\n+ * Syscall parameters taken from Qualcomm's LK fork (scm.h):\n+ * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.\n+ *\n+ * The PSCI implementation in the TrustZone/tz firmware on DragonBoard 410c has\n+ * a bug that starts all other CPU cores in 32-bit mode unless the TZ syscall\n+ * that switches from 32-bit to 64-bit mode is executed at least once.\n+ *\n+ * Normally this happens inside Qualcomm's LK bootloader which runs in 32-bit\n+ * mode and uses the TZ syscall to boot a kernel in 64-bit mode. However, if\n+ * U-Boot is installed to the \"aboot\" partition (replacing LK) the switch to\n+ * 64-bit mode never happens since U-Boot is already running in 64-bit mode.\n+ *\n+ * A workaround for this \"PSCI bug\" is to execute the TZ syscall when entering\n+ * U-Boot. That way PSCI is made aware of the 64-bit switch and starts all other\n+ * CPU cores in 64-bit mode as well.\n+ */\n+#include <linux/arm-smccc.h>\n+\n+#define ARM_SMCCC_SIP32_FAST_CALL \\\n+\tARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, ARM_SMCCC_OWNER_SIP, 0)\n+\n+\t/*\n+\t * U-Boot might be started in EL2 or EL3 with custom firmware.\n+\t * In that case, we assume that the workaround is not necessary or is\n+\t * handled already by the alternative firmware. Using the syscall in EL2\n+\t * would demote U-Boot to EL1; in EL3 it would probably just crash.\n+\t */\n+\tmrs\tx0, CurrentEL\n+\tcmp\tx0, #(1 << 2)\t/* EL1 */\n+\tbne\treset\n+\n+\t/* Prepare TZ syscall parameters */\n+\tmov\tx0, #ARM_SMCCC_SIP32_FAST_CALL\n+\tmovk\tx0, #0x10f\t/* SCM_SVC_MILESTONE_CMD_ID */\n+\tmov\tx1, #0x12\t/* MAKE_SCM_ARGS(0x2, SMC_PARAM_TYPE_BUFFER_READ) */\n+\tadr\tx2, el1_system_param\n+\tmov\tx3, el1_system_param_end - el1_system_param\n+\n+\t/* Switch PSCI to 64-bit mode. Resets CPU and returns at el1_elr */\n+\tsmc\t#0\n+\n+\t/* Something went wrong, perhaps PSCI is already in 64-bit mode? */\n+\tb\treset\n+\n+\t.align\t3\n+el1_system_param:\n+\t.quad\t0, 0, 0, 0, 0, 0, 0, 0, 0\t/* el1_x0-x8 */\n+\t.quad\treset\t\t\t\t/* el1_elr */\n+el1_system_param_end:\n", "prefixes": [ "v2", "04/10" ] }