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GET /api/1.2/patches/2221917/?format=api
{ "id": 2221917, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221917/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260410091154.1001021-6-varadarajan.narayanan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410091154.1001021-6-varadarajan.narayanan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-10T09:11:50", "name": "[v2,5/9] misc: qcom_geni: Add minicore support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1b9f56d28397c75c27da3201969800d17e1b1f4c", "submitter": { "id": 92283, "url": "http://patchwork.ozlabs.org/api/1.2/people/92283/?format=api", "name": "Varadarajan Narayanan", "email": "varadarajan.narayanan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.2/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260410091154.1001021-6-varadarajan.narayanan@oss.qualcomm.com/mbox/", "series": [ { "id": 499455, "url": "http://patchwork.ozlabs.org/api/1.2/series/499455/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499455", "date": "2026-04-10T09:11:45", "name": "Qualcomm IPQ5210 SoC bringup", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499455/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221917/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221917/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UeaZjrBa;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Q14JWswI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"UeaZjrBa\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"Q14JWswI\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscGg1pY5z1yGS\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 22:55:23 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 1CFAC841F2;\n\tFri, 10 Apr 2026 14:54:25 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 2587384106; Fri, 10 Apr 2026 11:13:16 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id A14B383DC9\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 11:13:13 +0200 (CEST)", "from pps.filterd (m0279871.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63A5LWFW2698258\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 09:13:12 GMT", "from mail-pj1-f72.google.com (mail-pj1-f72.google.com\n [209.85.216.72])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4degt9tg0c-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 09:13:11 +0000 (GMT)", "by mail-pj1-f72.google.com with SMTP id\n 98e67ed59e1d1-35678f99c6eso1521427a91.1\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 02:13:11 -0700 (PDT)", "from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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philip.molloy@analog.com,\n sughosh.ganu@arm.com, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v2 5/9] misc: qcom_geni: Add minicore support", "Date": "Fri, 10 Apr 2026 14:41:50 +0530", "Message-Id": "<20260410091154.1001021-6-varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260410091154.1001021-1-varadarajan.narayanan@oss.qualcomm.com>", "References": "<20260410091154.1001021-1-varadarajan.narayanan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDEwMDA4MSBTYWx0ZWRfX0xMw/ppXtdOW\n QDS7FE6ljzLxNiQgmR3sUCGONgQDlH8Q2QW6sfgmwz2DbhksqKFv91VR4+xV53aU4gX0mgbV6XI\n WsaIbsLwN613IhvkCS+48fcn4/HxzGyxSSh/XkLQMFaxZR+mDowmH41uDzkgAvbuRRsEvlLI3TF\n R8SDmQ0UY2INfoJosLXEPVJ1k2rjyRbD/+Mnzk+WhAHdYEW7ofVEk1EYGuLzMCYxzxMdqXsHsV5\n WlgYyotSldYUYAYAPjhuqYBIJq0QgPLG45FAfX+8vrdcabCSOX0Ft4i1SIQeP2VVBTbuKoUZWon\n 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"Clean" }, "content": "The qcom_geni driver reads an ELF from storage and configures a set of\nregisters and programs the firmware to the GENI Serial Engine (GENI-SE)\nwrapper device for the expected functionality.\n\nUnlike the GENI-SE wrapper found in MSM SoCs, the IPQ5210's GENI-SE\nwrapper is pre-configured for one of the functions defined in 'enum\ngeni_se_protocol_type'. Hence, the firmware download is not needed.\nOnly the register configuration part is needed.\n\nEarlier, the boot stages before U-Boot would configure the GENI-SE (to\naccess UART/SPI etc). Since for IPQ5210 U-Boot SPL, the previous stage\n(i.e. boot ROM) doesn't do that modify the driver to do the register\nconfiguration part alone without reading an ELF from the storage.\n\nSigned-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\n---\nv2: * Add CONFIG_QCOM_GENI_MINICORE option\n * Move register settings to separate file and include if\n CONFIG_QCOM_GENI_MINICORE is defined\n * Remove duplicate definition of GEN_USE_MINICORES\n * s/GEN_USE_MINICORES/GENI_USE_MINICORES\n * Skip find_qupfw_part() if it is a minicore\n---\n drivers/misc/Kconfig | 6 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/qcom_geni-minicore.c | 102 ++++++++++++++++++++++++++++++\n drivers/misc/qcom_geni.c | 90 ++++++++++++++++++++++----\n include/soc/qcom/geni-se.h | 2 +\n include/soc/qcom/qup-fw-load.h | 15 +++++\n 6 files changed, 204 insertions(+), 12 deletions(-)\n create mode 100644 drivers/misc/qcom_geni-minicore.c", "diff": "diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex ea785793d18..4bf75ecf5c7 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -93,6 +93,12 @@ config QCOM_GENI\n \t for providing a common interface for various peripherals like UART, I2C, SPI,\n \t etc.\n \n+config QCOM_GENI_MINICORE\n+\tbool \"Support minicores in Qualcomm Generic Interface (GENI) driver\"\n+\tdepends on QCOM_GENI\n+\thelp\n+\t Enable support for minicores in Qualcomm GENI and it's peripherals.\n+\n config ROCKCHIP_EFUSE\n bool \"Rockchip e-fuse support\"\n \tdepends on MISC\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex e2170212e5a..2daccbba74d 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -66,6 +66,7 @@ obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o\n obj-$(CONFIG_SANDBOX) += qfw_sandbox.o\n endif\n obj-$(CONFIG_QCOM_GENI) += qcom_geni.o\n+obj-$(CONFIG_QCOM_GENI_MINICORE) += qcom_geni-minicore.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o\ndiff --git a/drivers/misc/qcom_geni-minicore.c b/drivers/misc/qcom_geni-minicore.c\nnew file mode 100644\nindex 00000000000..33bc61ddf35\n--- /dev/null\n+++ b/drivers/misc/qcom_geni-minicore.c\n@@ -0,0 +1,102 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <soc/qcom/geni-se.h>\n+#include <soc/qcom/qup-fw-load.h>\n+\n+/*\n+ * Register configuration for the QUP minicores to setup the corresponding\n+ * functionality of SPI/I2C/UART.\n+ */\n+static u8 cfg_reg_idx[] = {\n+\t/* 0 to 18 */\n+\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n+\t/* 64 to 113 */\n+\t64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,\n+\t81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\n+\t98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\n+\t112, 113,\n+};\n+\n+static u32 spi_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00240E78, 0x00011088,\n+\t0x00240007, 0x00000000, 0x00000000, 0x0001000A, 0x00000300, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00154400, 0x001483A0, 0x00AA8128, 0x00641002,\n+\t0x00004000,\n+\t/* 64 to 113 */\n+\t0x00000201, 0x0001FE05, 0x0002C2E7, 0x0A435C00, 0x0010011A, 0x08800000,\n+\t0x00000000, 0x100CAC00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000018E4, 0x00000000,\n+\t0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x0007F807, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00200000, 0x00000004, 0x00000009, 0x0007F807, 0x000FFEFE, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00C0033F, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+static u32 uart_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000024, 0x00000000, 0x00000024, 0x00000000, 0x00019A00, 0x00400000,\n+\t0x00E00000, 0x00010020, 0x00000000, 0x00000000, 0x00000300, 0x00000700,\n+\t0x00000400, 0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00C00024,\n+\t0x00000B00,\n+\t/* 64 to 113 */\n+\t0x00020231, 0x0000CE05, 0x000360E7, 0x0941E6A8, 0x00100510, 0x42C01E51,\n+\t0x00000401, 0x002E8400, 0x1694581A, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x0000031C, 0x00000000,\n+\t0x0000000F, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00081C06, 0x00004010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x0000000D, 0x00000000, 0x00081C06, 0x00004010, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00C02415, 0x0000000E, 0x00000001,\n+\t0x00000001, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+static u32 i2c_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000090, 0x00000000, 0x00000090, 0x00000000, 0x00038028, 0x00084080,\n+\t0x00000343, 0x00010000, 0x00000000, 0x00001A00, 0x00000100, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00808008, 0x001C0020, 0x00000000, 0x00020000,\n+\t0x00000000,\n+\t/* 64 to 113 */\n+\t0x00000201, 0x0001FC01, 0x00036222, 0x09C01FFC, 0x00100120, 0x02C00000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000409, 0x00000003,\n+\t0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x0007F8FE, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000001, 0x0007F807, 0x000FFEFE, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+struct qup_mini_core_info qup_mini_cores[] = {\n+\t{\n+\t\t.serial_protocol = GENI_SE_SPI,\n+\t\t.fw_version = 0xb02,\n+\t\t.cfg_version = 0x9,\n+\t\t.cfg_count = ARRAY_SIZE(spi_cfg_val),\n+\t\t.cfg_val = spi_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_UART,\n+\t\t.fw_version = 0x405,\n+\t\t.cfg_version = 0xa,\n+\t\t.cfg_count = ARRAY_SIZE(uart_cfg_val),\n+\t\t.cfg_val = uart_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_I2C,\n+\t\t.fw_version = 0x204,\n+\t\t.cfg_version = 0x9,\n+\t\t.cfg_count = ARRAY_SIZE(i2c_cfg_val),\n+\t\t.cfg_val = i2c_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_INVALID_PROTO,\n+\t},\n+};\ndiff --git a/drivers/misc/qcom_geni.c b/drivers/misc/qcom_geni.c\nindex a62ae6a2478..bd27b29f7b6 100644\n--- a/drivers/misc/qcom_geni.c\n+++ b/drivers/misc/qcom_geni.c\n@@ -34,8 +34,15 @@ struct qup_se_rsc {\n \n struct geni_se_plat {\n \tbool need_firmware_load;\n+#if IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)\n+\tbool is_mini_core;\n+#endif\n };\n \n+#if IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)\n+extern struct qup_mini_core_info qup_mini_cores[];\n+#endif\n+\n /**\n * geni_enable_interrupts() Enable interrupts.\n * @rsc: Pointer to a structure representing SE-related resources.\n@@ -163,16 +170,44 @@ static void geni_config_common_control(struct qup_se_rsc *rsc)\n \t\t COMMON_CSR_SLV_CLK_CGC_ON_BMASK);\n }\n \n-static int load_se_firmware(struct qup_se_rsc *rsc, struct elf_se_hdr *hdr)\n+static int load_se_firmware(struct qup_se_rsc *rsc, bool elf, void *info)\n {\n+\tstruct elf_se_hdr *hdr, tmp_hdr;\n \tconst u32 *fw_val_arr, *cfg_val_arr;\n \tconst u8 *cfg_idx_arr;\n \tu32 i, reg_value, mask, ramn_cnt;\n \tint ret;\n \n-\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n-\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n-\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n+\tif (elf) {\n+\t\thdr = info;\n+\t\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n+\t\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n+\t\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n+\t} else if (IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)) {\n+\t\t/*\n+\t\t * Minicore controllers come with pre-configured functionality\n+\t\t * and don't need a firmware download and just need the register\n+\t\t * configuration. Hence, skipping the firmware part and setting\n+\t\t * up just the register configuration related information.\n+\t\t */\n+\t\tstruct qup_mini_core_info *qmc = info;\n+\n+\t\tfor (; qmc->serial_protocol != GENI_SE_INVALID_PROTO; qmc++)\n+\t\t\tif (qmc->serial_protocol == rsc->protocol)\n+\t\t\t\tbreak;\n+\n+\t\ttmp_hdr.magic = MAGIC_NUM_SE;\n+\t\ttmp_hdr.version = 1;\n+\t\ttmp_hdr.serial_protocol = rsc->protocol;\n+\t\ttmp_hdr.fw_version = qmc->fw_version;\n+\t\ttmp_hdr.cfg_version = qmc->cfg_version;\n+\t\ttmp_hdr.fw_size_in_items = qmc->cfg_ram_count;\n+\t\ttmp_hdr.cfg_size_in_items = qmc->cfg_count;\n+\t\thdr = &tmp_hdr;\n+\t\tfw_val_arr = (const u32 *)qmc->cfg_ram;\n+\t\tcfg_idx_arr = (const u8 *)qmc->cfg_idx;\n+\t\tcfg_val_arr = (const u32 *)qmc->cfg_val;\n+\t}\n \n \tgeni_config_common_control(rsc);\n \n@@ -350,8 +385,9 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n {\n \tstruct qup_se_rsc rsc;\n \tstruct elf_se_hdr *hdr;\n+\tbool elf;\n \tint ret;\n-\tvoid *fw;\n+\tvoid *fw, *info;\n \n \trsc.dev = dev;\n \trsc.base = qup_base;\n@@ -377,15 +413,22 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n \t/* The firmware blob is the private data of the GENI wrapper (parent) */\n \tfw = dev_get_priv(dev->parent);\n \n-\tret = read_elf(&rsc, fw, &hdr);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n-\t\treturn ret;\n+\tif (IS_ELF(*(Elf32_Ehdr *)fw)) {\n+\t\tret = read_elf(&rsc, fw, &hdr);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\telf = 1;\n+\t\tinfo = hdr;\n+\t} else {\n+\t\telf = 0;\n+\t\tinfo = fw;\n \t}\n \n \tdev_info(dev, \"Loading QUP firmware...\\n\");\n \n-\treturn load_se_firmware(&rsc, hdr);\n+\treturn load_se_firmware(&rsc, elf, info);\n }\n \n /*\n@@ -414,6 +457,11 @@ static int geni_se_of_to_plat(struct udevice *dev)\n \n \t\tif (proto == GENI_SE_INVALID_PROTO)\n \t\t\tplat->need_firmware_load = true;\n+\n+#if IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)\n+\t\tif (readl(res.start + QUPV3_SE_HW_PARAM_2) & GENI_USE_MINICORES)\n+\t\t\tplat->is_mini_core = true;\n+#endif\n \t}\n \n \treturn 0;\n@@ -473,7 +521,7 @@ static int probe_children_load_firmware(struct udevice *dev)\n \t\tret = 0;\n \t\t/* Find the device for this ofnode, or bind it */\n \t\tif (device_find_global_by_ofnode(child, &child_dev))\n-\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\t\n+\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\n \t\tif (ret) {\n \t\t\t/* Skip nodes that don't have drivers */\n \t\t\tdebug(\"Failed to probe child %s: %d\\n\", ofnode_get_name(child), ret);\n@@ -492,7 +540,11 @@ static int probe_children_load_firmware(struct udevice *dev)\n * Load firmware for QCOM GENI peripherals from the dedicated partition on storage and bind/probe\n * all the peripheral devices that need firmware to be loaded.\n */\n-static int qcom_geni_fw_initialise(void)\n+#if CONFIG_XPL_BUILD\n+int qcom_geni_fw_initialise(struct udevice *dev)\n+#else\n+int qcom_geni_fw_initialise(void)\n+#endif\n {\n \tdebug(\"Loading firmware for QCOM GENI SE\\n\");\n \tstruct udevice *geni_wrapper, *blk_dev;\n@@ -518,6 +570,12 @@ static int qcom_geni_fw_initialise(void)\n \t\treturn 0;\n \t}\n \n+#if IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)\n+\tif (plat->is_mini_core) {\n+\t\tfw_buf = qup_mini_cores;\n+\t\tgoto mini_core;\n+\t}\n+#endif\n \tret = find_qupfw_part(&blk_dev, &part_info);\n \tif (ret) {\n \t\tpr_err(\"QUP firmware partition not found\\n\");\n@@ -544,6 +602,9 @@ static int qcom_geni_fw_initialise(void)\n \t\treturn 0;\n \t}\n \n+#if IS_ENABLED(CONFIG_QCOM_GENI_MINICORE)\n+mini_core:\n+#endif\n \t/*\n \t * OK! Firmware is loaded, now bind and probe remaining children. They will attempt to load\n \t * firmware during probe. Do this for each GENI SE wrapper that needs firmware loading.\n@@ -563,7 +624,9 @@ static int qcom_geni_fw_initialise(void)\n \treturn 0;\n }\n \n+#if !CONFIG_XPL_BUILD\n EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qcom_geni_fw_initialise);\n+#endif\n \n static const struct udevice_id geni_ids[] = {\n \t{ .compatible = \"qcom,geni-se-qup\" },\n@@ -577,4 +640,7 @@ U_BOOT_DRIVER(geni_se_qup) = {\n \t.of_to_plat = geni_se_of_to_plat,\n \t.plat_auto = sizeof(struct geni_se_plat),\n \t.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,\n+#if CONFIG_XPL_BUILD\n+\t.probe = qcom_geni_fw_initialise,\n+#endif\n };\ndiff --git a/include/soc/qcom/geni-se.h b/include/soc/qcom/geni-se.h\nindex fc9a8e82cd8..94f3e5c8c7e 100644\n--- a/include/soc/qcom/geni-se.h\n+++ b/include/soc/qcom/geni-se.h\n@@ -77,6 +77,7 @@ enum geni_se_protocol_type {\n #define SE_IRQ_EN\t\t\t0xe1c\n #define SE_HW_PARAM_0\t\t\t0xe24\n #define SE_HW_PARAM_1\t\t\t0xe28\n+#define SE_HW_PARAM_2\t\t\t0xe2c\n #define SE_DMA_GENERAL_CFG\t\t0xe30\n \n /* GENI_DFS_IF_CFG fields */\n@@ -248,6 +249,7 @@ enum geni_se_protocol_type {\n /* SE_HW_PARAM_0 fields */\n #define TX_FIFO_WIDTH_MSK\t\tGENMASK(29, 24)\n #define TX_FIFO_WIDTH_SHFT\t\t24\n+\n /*\n * For QUP HW Version >= 3.10 Tx fifo depth support is increased\n * to 256bytes and corresponding bits are 16 to 23\ndiff --git a/include/soc/qcom/qup-fw-load.h b/include/soc/qcom/qup-fw-load.h\nindex a67a93c72a4..4e876e650a2 100644\n--- a/include/soc/qcom/qup-fw-load.h\n+++ b/include/soc/qcom/qup-fw-load.h\n@@ -14,6 +14,7 @@\n #define GENI_INIT_CFG_REVISION\t\t0x0\n #define GENI_S_INIT_CFG_REVISION\t0x4\n #define GENI_FORCE_DEFAULT_REG\t\t0x20\n+#define GENI_OUTPUT_CTRL\t\t0x24\n #define GENI_CGC_CTRL\t\t\t0x28\n #define GENI_CFG_REG0\t\t\t0x100\n \n@@ -21,6 +22,9 @@\n #define RX_FIFO_WIDTH_BIT\t\t24\n #define RX_FIFO_WIDTH_MASK\t\t0x3F\n \n+#define QUPV3_SE_HW_PARAM_2\t\t0xe2c\n+#define GENI_USE_MINICORES\t\tBIT(12)\n+\n /*Same registers as GENI_DMA_MODE_EN*/\n #define QUPV3_SE_GENI_DMA_MODE_EN\t0x258\n #define GENI_M_IRQ_ENABLE\t\t0x614\n@@ -173,6 +177,17 @@ struct elf_se_hdr {\n \n struct udevice;\n \n+struct qup_mini_core_info {\n+\tu16 serial_protocol;\n+\tu16 fw_version;\n+\tu16 cfg_version;\n+\tu16 cfg_count;\n+\tu32 *cfg_val;\n+\tu8 *cfg_idx;\n+\tu32 *cfg_ram;\n+\tu32 cfg_ram_count;\n+};\n+\n int qcom_geni_load_firmware(phys_addr_t qup_base, struct udevice *dev);\n \n #endif /* _LINUX_QCOM_QUP_FW_LOAD */\n", "prefixes": [ "v2", "5/9" ] }