Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2221915/?format=api
{ "id": 2221915, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221915/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260410091154.1001021-4-varadarajan.narayanan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410091154.1001021-4-varadarajan.narayanan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-10T09:11:48", "name": "[v2,3/9] clk/qcom: add initial clock driver for ipq5210", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3783cd0d4559d6ccee77856e160905ea31a40421", "submitter": { "id": 92283, "url": "http://patchwork.ozlabs.org/api/1.2/people/92283/?format=api", "name": "Varadarajan Narayanan", "email": "varadarajan.narayanan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.2/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260410091154.1001021-4-varadarajan.narayanan@oss.qualcomm.com/mbox/", "series": [ { "id": 499455, "url": "http://patchwork.ozlabs.org/api/1.2/series/499455/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499455", "date": "2026-04-10T09:11:45", "name": "Qualcomm IPQ5210 SoC bringup", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499455/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221915/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221915/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=lr3dmVVT;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=VOkFWOt4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"lr3dmVVT\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"VOkFWOt4\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscGJ1JXzz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 22:55:04 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9CAEF841CD;\n\tFri, 10 Apr 2026 14:54:24 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 6F6E684106; Fri, 10 Apr 2026 11:12:52 +0200 (CEST)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1C0E283DC9\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 11:12:49 +0200 (CEST)", "from pps.filterd (m0279867.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63A75cA81729914\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 09:12:48 GMT", "from mail-pj1-f71.google.com (mail-pj1-f71.google.com\n [209.85.216.71])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deckxkjmd-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 09:12:47 +0000 (GMT)", "by mail-pj1-f71.google.com with SMTP id\n 98e67ed59e1d1-354490889b6so2956637a91.3\n for <u-boot@lists.denx.de>; Fri, 10 Apr 2026 02:12:47 -0700 (PDT)", "from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19])\n by smtp.gmail.com with ESMTPSA id\n 98e67ed59e1d1-35e4123a29fsm2564871a91.8.2026.04.10.02.12.35\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 10 Apr 2026 02:12:46 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=EeMcpicEVGz\n 26VJ4q6kUTiEUTbBHjltnzjtT0vSHomI=; b=lr3dmVVTFu0xsnsktGV4nfH28zf\n m/eLOhnjPbAn9BwRZFAxD5wX1BWkbAwQNvgYLDbvelng3oJlbGa+qxemgwpXSCtu\n XBf+KD9SfXk10XnhDVcUfn44KjlHUScx9pVDRFU/IiyAbT/M7SuvjPMml8i4wQko\n hTHbA+H4syWUe11x3jUmMG8SLlkqpRA0WPvIjYksjo8+XAOvfvapqmONapt+GdAF\n UyWNeGdiRTmSBDrt9me6qSPIS7gomW7Hz5LxDzRtHXN0oYjBg31ym1O3u96t3qTp\n U98KQrWqfoSDrHAr+ieOV0j0dMrme4dURULFd+5puvEo5vODxZfwki4CUzg==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775812367; x=1776417167; darn=lists.denx.de;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=EeMcpicEVGz26VJ4q6kUTiEUTbBHjltnzjtT0vSHomI=;\n b=VOkFWOt4ku5hWZb6TIDqvIB/T6Q6vAiz6uV8/hlsT8L0c5z9KziMFdU2r2pVQnZlm7\n W1QNMhbpUYuZ/nru4MaVngzpKCgEFk/SohM43vr4+2W1BGHxyVhfcct+U/aDZOcnt5qH\n +EhrF+C1A2E0ULeApqDaHoRq3tTGYdXGKUPUoD5JCbiWTXKjSLGvxO0EjHLFGXfISFYW\n T6IJoEoUwCTI4jwkPeIOc+LafcYCt3doyIXZOdTbm2JIoVQos0HwUYi7hCqrndfhtsUm\n Y3eTEyPxJdnGPczIyZfEkTswDi1FIU5IWaamBNC/BhLUmJtpiJy6N2cY7IK5bZ8NQvCk\n kiQw==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775812367; x=1776417167;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=EeMcpicEVGz26VJ4q6kUTiEUTbBHjltnzjtT0vSHomI=;\n b=Ed0nUXDEG1qMtv1uLpkFu2CPB0d2mL9LHzbpAIiFMJx5T86xBIF3vPvNpqSqgXP+5a\n EsDawfpp/rD5LHX+dSRssDhHqO3a5nDf3nBQAXbtiWMX0CT48gQezPf7nfh+h+JshyH5\n 37rS4Txae/hK9A6+AslCRVJ65XJ/NiAgebPr7ndsKlA/7OkXGwbgO94J2R62FGsfuWYr\n 8o9Le++RIt01HTWucLUguJvVxaIhlT/35QkKk1hTBo0J7D1e7bzPnJHo8wlCxTNzYJSL\n LYrA4Vvja+6OQtdFuqlZPO5qq6GXoSqDbz7inGeooS6Z/b5G7grc8N6SICWFUD4IIe2D\n X1Lw==", "X-Forwarded-Encrypted": "i=1;\n AJvYcCVfl6VFg+mP/RnnC2WvLmrspg0gdKWzt6GDYxdOwTXyZXnjCql435u9xs9uwmsPj6we0SLGNpE=@lists.denx.de", "X-Gm-Message-State": "AOJu0YxFMDyrPjXOnQqf8yStOzQK04iDZ1lh8TpbiYS1+xo4eL0Cm0BN\n qo4VKtSxrk7AbA+UsFIMQy0WJGzj/Ezu0Kz6l2/slz2wtYoFKE3FajewTEKQT5lNWcWwvu1zJiP\n XZMNXivDRpb3M+ZhMnHJdXmU/tXOlKU5fb3I6bJWfZsxQuuYWU29YpH1p", "X-Gm-Gg": "AeBDiesLh6Qjjs98GW3v/+xXil/8zs8duLknTHaYbYYicWHMwNejzvyU/XrsHgrzR4K\n BHMY2ASu6VCZNC4AK5az1eomNdTo8pVAQZNMRd/Dn3roJYo3iSTFjzrNh/56fYgjmMjZ8nMpqDH\n iNHw7ckY0eP6f2E8oEmkg7WRn827REf3UGzKmAEkEOoqvNuCduPESOmoI69aBgZ2C4zgtlfpw7q\n OJoBNWwnlb1xefDGzY0aN9B0w7RoZNK3usYWvDlbIpZZECbaF/8CtglJSDIK0EPoPZCd9TrIJQ2\n R3Aw8Z0Bbv9Gz+sQoEC0lHXqVG8+zvh4WhbA1z93o3cXd/aovMc5Un/B//m8uVpDUgrF24o57pT\n GCfaz9X9VLiJXClNNOexs16Iwb+ald4Oq3n9F13dJiYs2SUBLyeGIZxbU2u+i3lyQSnfc8TTPch\n sJPw6/O2gjni5SRuQ4MdJa6iT8bngjJ8RP5+LzihOd4H7KfOwkcFw=", "X-Received": [ "by 2002:a17:90b:3dc7:b0:35c:8ac:ef74 with SMTP id\n 98e67ed59e1d1-35e42747d34mr2628457a91.6.1775812367106;\n Fri, 10 Apr 2026 02:12:47 -0700 (PDT)", "by 2002:a17:90b:3dc7:b0:35c:8ac:ef74 with SMTP id\n 98e67ed59e1d1-35e42747d34mr2628432a91.6.1775812366564;\n Fri, 10 Apr 2026 02:12:46 -0700 (PDT)" ], "From": "Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>", "To": "rayagonda.kokatanur@broadcom.com, trini@konsulko.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, peng.fan@nxp.com, jh80.chung@samsung.com,\n lukma@denx.de, tien.fong.chee@altera.com, anshuld@ti.com,\n alif.zakuan.yuslaimi@altera.com, tingting.meng@altera.com,\n alice.guo@nxp.com, quentin.schulz@cherry.de,\n ilias.apalodimas@linaro.org, varadarajan.narayanan@oss.qualcomm.com,\n xypron.glpk@gmx.de, mkorpershoek@kernel.org, h-salunke@ti.com,\n alchark@gmail.com, dario.binacchi@amarulasolutions.com, ye.li@nxp.com,\n andre.przywara@arm.com, afd@ti.com, dinesh.maniyam@altera.com,\n balaji.selvanathan@oss.qualcomm.com, danila@jiaxyga.com,\n aswin.murugan@oss.qualcomm.com, luca.weiss@fairphone.com,\n adrian@mainlining.org, justin@tidylabs.net, n-francis@ti.com,\n wens@kernel.org, jamie.gibbons@microchip.com,\n david.wronek@mainlining.org, alexeymin@postmarketos.org,\n james.hilliard1@gmail.com, michael@amarulasolutions.com,\n richard.genoud@bootlin.com, philip.molloy@analog.com,\n sughosh.ganu@arm.com, u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v2 3/9] clk/qcom: add initial clock driver for ipq5210", "Date": "Fri, 10 Apr 2026 14:41:48 +0530", "Message-Id": "<20260410091154.1001021-4-varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260410091154.1001021-1-varadarajan.narayanan@oss.qualcomm.com>", "References": "<20260410091154.1001021-1-varadarajan.narayanan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "yMfynA8gIV7jOSbfrSq9LBTl6JepTWUl", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDEwMDA4MSBTYWx0ZWRfX6aop5qHer3nx\n UysnpD/XzBF1jSUuQ5/jlq9W/Mrauf3X5B3FWvADyQDXo4ED0OHKvcEJgJVo0xYHQ5H17Ty6DCG\n Lsh7GepBx8CZmJKjiJlOrfI4aL9fCu7gKOWaiGvBh+CVmBE5XtvgxarWliCc4MKVnhpHLSbTqS8\n T/vP0V8v3ugCVR/Jbq10tsN5B6w/laaj5f0wAXJjROuzqOaeHXq21FTacEJ70yMSZP9ZksVAsJN\n iB6QcTC23QX4Km+QrpIby1QF0cytFw7uR2Qg5op/nyx2KivjnKBJoRuvUSvoZuS+YvzYKdAUDnj\n CCYV9J/cx5NfpM2BFh6jketpAwv+C9BOb3p1sF7fgzfkEa76VEYT2sml+pFb5vaWp1tuL/O9XVI\n 923mrn/8Mze9RLqUmzuIiloVR0GGGXdxDOb2RsJ3j8CcRt8bMl0W33cN+V9LUCfMBMea4l7E/W2\n rF7NqtAcxGKjgGcTw1w==", "X-Authority-Analysis": "v=2.4 cv=OMcXGyaB c=1 sm=1 tr=0 ts=69d8bf0f cx=c_pps\n a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8\n a=ttnG5VEth79ohM5wMFYA:9 a=tjWZ8NC-rebGB_hs:21 a=uKXjsCUrEbL0IQVhDsJ9:22", "X-Proofpoint-GUID": "yMfynA8gIV7jOSbfrSq9LBTl6JepTWUl", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-10_02,2026-04-09_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0\n priorityscore=1501 lowpriorityscore=0 suspectscore=0 malwarescore=0\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604100081", "X-Mailman-Approved-At": "Fri, 10 Apr 2026 14:54:22 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add initial set of clocks and resets for enabling U-Boot on ipq5210\nbased RDP platforms.\n\nSigned-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\n---\n drivers/clk/qcom/Kconfig | 8 +++\n drivers/clk/qcom/Makefile | 1 +\n drivers/clk/qcom/clock-ipq5210.c | 97 ++++++++++++++++++++++++++++++++\n 3 files changed, 106 insertions(+)\n create mode 100644 drivers/clk/qcom/clock-ipq5210.c", "diff": "diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 8504ed5d656..a0a8778d5f0 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019\n \t on the Snapdragon IPQ4019 SoC. This driver supports the clocks\n \t and resets exposed by the GCC hardware block.\n \n+config CLK_QCOM_IPQ5210\n+\tbool \"Qualcomm IPQ5210 GCC\"\n+\tselect CLK_QCOM\n+\thelp\n+\t Say Y here to enable support for the Global Clock Controller\n+\t on the Qualcomm IPQ5210 SoC. This driver supports the clocks\n+\t and resets exposed by the GCC hardware block.\n+\n config CLK_QCOM_IPQ5424\n \tbool \"Qualcomm IPQ5424 GCC\"\n \tselect CLK_QCOM\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex 82a5b166196..7116be963e7 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o\n obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o\n obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o\n obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o\n+obj-$(CONFIG_CLK_QCOM_IPQ5210) += clock-ipq5210.o\n obj-$(CONFIG_CLK_QCOM_IPQ5424) += clock-ipq5424.o\n obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o\n obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o\ndiff --git a/drivers/clk/qcom/clock-ipq5210.c b/drivers/clk/qcom/clock-ipq5210.c\nnew file mode 100644\nindex 00000000000..f0a6ee8711d\n--- /dev/null\n+++ b/drivers/clk/qcom/clock-ipq5210.c\n@@ -0,0 +1,97 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Clock drivers for Qualcomm IPQ5210\n+ *\n+ * (C) Copyright 2024 Linaro Ltd.\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <linux/types.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <linux/delay.h>\n+#include <asm/io.h>\n+#include <linux/bug.h>\n+#include <linux/bitops.h>\n+#include <dm/device-internal.h>\n+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>\n+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>\n+#include \"clock-qcom.h\"\n+\n+static ulong ipq5210_set_rate(struct clk *clk, ulong rate)\n+{\n+\tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\n+\tswitch (clk->id) {\n+\tcase GCC_QUPV3_WRAP_SE1_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n+\t\t\t\t 0, 2, 217, CFG_CLK_SRC_GPLL0, 16);\n+\t\tbreak;\n+\tcase GCC_SDCC1_AHB_CLK:\n+\t\tbreak;\n+\tcase GCC_SDCC1_APPS_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].cbcr_reg,\n+\t\t\t\t 0, 6, 25, CFG_CLK_SRC_GPLL0, 16);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn rate;\n+}\n+\n+static const struct gate_clk ipq5210_clks[] = {\n+\tGATE_CLK_POLLED(GCC_QUPV3_WRAP_SE1_CLK,\t0x05020, BIT(0),\t0x05004),\n+\tGATE_CLK_POLLED(GCC_SDCC1_AHB_CLK,\t0x3303c, BIT(0),\t0x3303c),\n+\tGATE_CLK_POLLED(GCC_SDCC1_APPS_CLK,\t0x3302c, BIT(0),\t0x33004),\n+\tGATE_CLK_POLLED(GCC_IM_SLEEP_CLK,\t0x34020, BIT(0),\t0x34020),\n+};\n+\n+static int ipq5210_enable(struct clk *clk)\n+{\n+\tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n+\n+\tif (priv->data->num_clks <= clk->id) {\n+\t\tdebug(\"%s: unknown clk id %lu\\n\", __func__, clk->id);\n+\t\treturn 0;\n+\t}\n+\n+\tdebug(\"%s: clk %s\\n\", __func__, ipq5210_clks[clk->id].name);\n+\n+\tqcom_gate_clk_en(priv, clk->id);\n+\n+\treturn 0;\n+}\n+\n+static const struct qcom_reset_map ipq5210_gcc_resets[] = {\n+\t[GCC_SDCC_BCR]\t\t\t= {0x33000, 0},\n+\t[GCC_USB0_PHY_BCR]\t\t= {0x2c06c, 0},\n+\t[GCC_USB3PHY_0_PHY_BCR]\t\t= {0x2c070, 0},\n+\t[GCC_QUSB2_0_PHY_BCR]\t\t= {0x2c068, 0},\n+\t[GCC_USB_BCR]\t\t\t= {0x2c000, 0},\n+};\n+\n+static struct msm_clk_data ipq5210_gcc_data = {\n+\t.resets = ipq5210_gcc_resets,\n+\t.num_resets = ARRAY_SIZE(ipq5210_gcc_resets),\n+\t.clks = ipq5210_clks,\n+\t.num_clks = ARRAY_SIZE(ipq5210_clks),\n+\t.enable = ipq5210_enable,\n+\t.set_rate = ipq5210_set_rate,\n+};\n+\n+static const struct udevice_id gcc_ipq5210_of_match[] = {\n+\t{\n+\t\t.compatible = \"qcom,ipq5210-gcc\",\n+\t\t.data = (ulong)&ipq5210_gcc_data,\n+\t},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(gcc_ipq5210) = {\n+\t.name\t\t= \"gcc_ipq5210\",\n+\t.id\t\t= UCLASS_NOP,\n+\t.of_match\t= gcc_ipq5210_of_match,\n+\t.bind\t\t= qcom_cc_bind,\n+\t.flags\t\t= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,\n+};\n", "prefixes": [ "v2", "3/9" ] }