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GET /api/1.2/patches/2221631/?format=api
{ "id": 2221631, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221631/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-4-sherry.sun@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260410023055.2439146-4-sherry.sun@nxp.com>", "list_archive_url": null, "date": "2026-04-10T02:30:46", "name": "[V12,03/12] PCI: imx6: Assert PERST# before enabling regulators", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "62d1ebc7c98301a0f45a12b0e2759bcf378331ba", "submitter": { "id": 77063, "url": "http://patchwork.ozlabs.org/api/1.2/people/77063/?format=api", "name": "Sherry Sun", "email": "sherry.sun@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410023055.2439146-4-sherry.sun@nxp.com/mbox/", "series": [ { "id": 499380, "url": "http://patchwork.ozlabs.org/api/1.2/series/499380/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499380", "date": "2026-04-10T02:30:43", "name": "pci-imx6: Add support for parsing the reset property in new Root Port binding", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/499380/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221631/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52245-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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PvPfq0hQrOutZ3sYjZyrJs6b6IN1svsDMfSMxpQuwPJptV6ZfXhvsi+bNo3o8mmNwPeBc0GRsBmD+loLFhlBO98b0bppEX1IGbik/QCXt+EY2Qw5wP0tD3kHq2xejI0CeFbFMEa88sDnfYz6J4UUGTFPJ9wSdsDV+SXM+B+tLEhgixm0yzFQrAiF2hUIITe3Una2NZRuMEDxmdruj5IhG0tQkTgdWGv984IUp8FX9oSXo8wOLp/dZgt1U5yuiUWrmZ9aXUqr6eEWUCkxneYfuTUmcPkCA519KmderBpTBLSznPAIZOe+0vX1YanSuhSh49dsPWQWlx8BDFNkX96EO9mbUopxFQHD5bfmRcuO/d52USrBpQPPiCJnt95axKOOWYorw+/QJvrmF4rfWYqw0cp7k3ENHbzXktD0Lv+XSLtCXsNkVkeK5m9I2NT3woFgewrt7GNOs4lp1cUdKnGN02gW21rSFFs2KaY745fuUQr1T4t5K3IpbOdF02ObKh27Ade6L/m0pHYKhKgMyp+tETq9eMt9lEaMU/AdCVXzW+mkezLf0rQew2gk/ryV0ARqEHEgX+hzqwl1M5KsvElIGfXADxoFw2ZBNVJPPvo2Qjj/bQGu5VJgPoBuWmQZV3fzUi2y2AHhYVyEwCquxaU8bC/Ts2HqoeICnk4XweAE1/mKuwqO3Inrfn1pvcHEC24ek84+iTAXsBHCRL8PQs1QNR3EtBlE5T/OYduMoR4UUqmUCtcBw6eIVE6xLnspfziybkBw7YHx1hv+vSDD69NKpPjB8snSJ3W4O85OuTloam1ujAmhcrhAd59ifWyumd5R/e4CyQjH7hZbIkX/ATLOUAV9EjIOG+vwBm1vvAXG7p05W6+xsB+aP7dyT3yCxz3u/2ImcHedA5LFq0eOUi0/aIYZ1UPxXJtDw1TJzarVGTbt4UzLkzk/iPU0SbCteb8cNvGMwljuDQYewm+hkAr7v9yH5r/y6rkU13N5ScHu9DKXV4HZ5cn+uy6uJm9ZsPEr9xBRsU5dJ+MwSYp+sBCsgq7BCXxmAX1Bd/nf1fWcsEQssxaT2tflXnStchsBr+fWWTg9g0KDRlo1q38MNAY2XDbvcUAUgE62xLvHZTXa8ClIlJQ0YWWT3bGPT3i1MPWyRVZkXvAyGaVBEh/o//q77wVqsRYvBvs+iEK6ftSGDL2b+l5sBQTRIGHmVFUla06+dvDgpj2VyLMuKDKPIQJgdEWzUOSBRAMDIoTo1f+j6DKbO70mfjQTmOmkaV3dvjkXVPgqpo4L7dTIP2N81uyQUlJORlWXrYs0zFJxooY9RVk+CqCLXYdQfAXaXzYiinaqiBWvarHiLaN2stjQmGqeojoVXEYtneZf1FOXcS4WNOg6yoQgIF6H4lbjcA0AJNvnZv4NJrWM24zTExQmocMTFU85LZK4AlkeOjFUbiDY8uMVq5Q68S0xzmYThD+DAZ3FWORq5nsG0KF1W2LUVadxV36l7uZsDKKYvH7Lv59dXV61gv93AvEbnwrEDMAiD7ZtwnwzbY6xrZYeyexQiy1oEM7hzUKdD0E3oFfjODB12UsrWBMiQuqKB1LJ0eYgjR537SvTsH9d4WLvca1FQUYy2yp5Qn3Af02Z6ErcTK1K2/4rJm+wmWGefBtlWh29wxXTKWUFSzAJ6pFaDiw+B7DGtvI19+pIsg86dTegXxLzPUnbshrBBkDKYDAn4EcqRugYF7idmAE8fDL540A0tz/omg==", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a78ac298-cd06-4de6-e507-08de96a90c02", "X-MS-Exchange-CrossTenant-AuthSource": "VI0PR04MB12114.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Apr 2026 02:29:52.9682\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n kUYRISYHLrk0Yesz0npnmieClaf6FTzsF37oqSrPGPpixTMXFXI8Bs3zxyhhdEec6VXQtx1qcsQoGODE8HrwTw==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AS5PR04MB9826" }, "content": "The PCIe endpoint may start responding or driving signals as soon as\nits supply is enabled, even before the reference clock is stable.\nAsserting PERST# before enabling the regulator ensures that the\nendpoint remains in reset throughout the entire power-up sequence,\nuntil both power and refclk are known to be stable and link\ninitialization can safely begin.\n\nCurrently, the driver enables the vpcie3v3aux regulator in\nimx_pcie_probe() before PERST# is asserted in imx_pcie_host_init(),\nwhich may cause PCIe endpoint undefined behavior during early\npower-up. However, there is no issue so far because PERST# is\nrequested as GPIOD_OUT_HIGH in imx_pcie_probe(), which guarantees\nthat PERST# is asserted before enabling the vpcie3v3aux regulator.\n\nThis is prepare for the upcoming changes that will parse the reset\nproperty using the new Root Port binding, which will use GPIOD_ASIS\nwhen requesting the reset GPIO. With GPIOD_ASIS, the GPIO state is not\nguaranteed, so explicit sequencing is required.\n\nFix the power sequencing by:\n1. Moving vpcie3v3aux regulator enable from probe to\n imx_pcie_host_init(), where it can be properly sequenced with PERST#.\n2. Moving imx_pcie_assert_perst() before regulator and clock enable to\n ensure correct ordering.\n\nSigned-off-by: Sherry Sun <sherry.sun@nxp.com>\n---\n drivers/pci/controller/dwc/pci-imx6.c | 49 +++++++++++++++++++++------\n 1 file changed, 39 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex 915061ea75b9..d99da7e42590 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -168,6 +168,8 @@ struct imx_pcie {\n \tu32\t\t\ttx_swing_full;\n \tu32\t\t\ttx_swing_low;\n \tstruct regulator\t*vpcie;\n+\tstruct regulator\t*vpcie_aux;\n+\tbool\t\t\tvpcie_aux_enabled;\n \tstruct regulator\t*vph;\n \tvoid __iomem\t\t*phy_base;\n \n@@ -1222,6 +1224,13 @@ static void imx_pcie_disable_device(struct pci_host_bridge *bridge,\n \timx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev));\n }\n \n+static void imx_pcie_vpcie_aux_disable(void *data)\n+{\n+\tstruct regulator *vpcie_aux = data;\n+\n+\tregulator_disable(vpcie_aux);\n+}\n+\n static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert)\n {\n \tif (assert) {\n@@ -1242,6 +1251,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \tstruct imx_pcie *imx_pcie = to_imx_pcie(pci);\n \tint ret;\n \n+\timx_pcie_assert_perst(imx_pcie, true);\n+\n+\t/* Keep 3.3Vaux supply enabled for the entire PCIe controller lifecycle */\n+\tif (imx_pcie->vpcie_aux && !imx_pcie->vpcie_aux_enabled) {\n+\t\tret = regulator_enable(imx_pcie->vpcie_aux);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"failed to enable vpcie_aux regulator: %d\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\timx_pcie->vpcie_aux_enabled = true;\n+\n+\t\tret = devm_add_action_or_reset(dev, imx_pcie_vpcie_aux_disable,\n+\t\t\t\t\t imx_pcie->vpcie_aux);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tif (imx_pcie->vpcie) {\n \t\tret = regulator_enable(imx_pcie->vpcie);\n \t\tif (ret) {\n@@ -1251,25 +1278,24 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)\n \t\t}\n \t}\n \n+\tret = imx_pcie_clk_enable(imx_pcie);\n+\tif (ret) {\n+\t\tdev_err(dev, \"unable to enable pcie clocks: %d\\n\", ret);\n+\t\tgoto err_reg_disable;\n+\t}\n+\n \tif (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) {\n \t\tpp->bridge->enable_device = imx_pcie_enable_device;\n \t\tpp->bridge->disable_device = imx_pcie_disable_device;\n \t}\n \n \timx_pcie_assert_core_reset(imx_pcie);\n-\timx_pcie_assert_perst(imx_pcie, true);\n \n \tif (imx_pcie->drvdata->init_phy)\n \t\timx_pcie->drvdata->init_phy(imx_pcie);\n \n \timx_pcie_configure_type(imx_pcie);\n \n-\tret = imx_pcie_clk_enable(imx_pcie);\n-\tif (ret) {\n-\t\tdev_err(dev, \"unable to enable pcie clocks: %d\\n\", ret);\n-\t\tgoto err_reg_disable;\n-\t}\n-\n \tif (imx_pcie->phy) {\n \t\tret = phy_init(imx_pcie->phy);\n \t\tif (ret) {\n@@ -1782,9 +1808,12 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \tof_property_read_u32(node, \"fsl,max-link-speed\", &pci->max_link_speed);\n \timx_pcie->supports_clkreq = of_property_read_bool(node, \"supports-clkreq\");\n \n-\tret = devm_regulator_get_enable_optional(&pdev->dev, \"vpcie3v3aux\");\n-\tif (ret < 0 && ret != -ENODEV)\n-\t\treturn dev_err_probe(dev, ret, \"failed to enable Vaux supply\\n\");\n+\timx_pcie->vpcie_aux = devm_regulator_get_optional(&pdev->dev, \"vpcie3v3aux\");\n+\tif (IS_ERR(imx_pcie->vpcie_aux)) {\n+\t\tif (PTR_ERR(imx_pcie->vpcie_aux) != -ENODEV)\n+\t\t\treturn PTR_ERR(imx_pcie->vpcie_aux);\n+\t\timx_pcie->vpcie_aux = NULL;\n+\t}\n \n \timx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, \"vpcie\");\n \tif (IS_ERR(imx_pcie->vpcie)) {\n", "prefixes": [ "V12", "03/12" ] }