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GET /api/1.2/patches/2221518/?format=api
{ "id": 2221518, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221518/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409-ad4692-multichannel-sar-adc-driver-v7-6-be375d4df2c5@analog.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260409-ad4692-multichannel-sar-adc-driver-v7-6-be375d4df2c5@analog.com>", "list_archive_url": null, "date": "2026-04-09T15:28:27", "name": "[v7,6/6] docs: iio: adc: ad4691: add driver documentation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "84238ef9298925e9c7bbfda3fb54ef754a587d08", "submitter": { "id": 92791, "url": "http://patchwork.ozlabs.org/api/1.2/people/92791/?format=api", "name": "Radu Sabau via B4 Relay", "email": "devnull+radu.sabau.analog.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409-ad4692-multichannel-sar-adc-driver-v7-6-be375d4df2c5@analog.com/mbox/", "series": [ { "id": 499317, "url": "http://patchwork.ozlabs.org/api/1.2/series/499317/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499317", "date": "2026-04-09T15:28:22", "name": "iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/499317/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221518/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221518/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34964-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=rvjyhgJm;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775748509; cv=none;\n b=nFbqG2Mr/Pz7td0Nc8XQLt2RI9zakruCHDERPyD0QGeo0ZpW37tx5k7jkuB3i3WEIEp55xPYbT24GObN+MVBxlkrWKAG/XV7KlpCJU+tSRrYcdw+roI0gVYdaqpjpaCge730khwIURepCud/RXHzMA9q0XL9JnxRBwRAOf7yX2A=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775748509; c=relaxed/simple;\n\tbh=UKUNZNcLrasERkVlHShR61ZM9paPsd4OyfoQALpvaI8=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=T1Y37YdhHbJv1DCD+P97vCrEHPwFAv7tHcO/UoMTH/z+NL9P0b3HKEHqifPIdg19jGGjCAZjXeiM6oc1im4erauKZG2DDwNUb4PHVv6Bx5P7wzS+n6w7DvAXVboj20hOc1PsqyrMheiBahkrRzmDZdg109pbLc9s807UNi7y4TE=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=rvjyhgJm; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775748509;\n\tbh=UKUNZNcLrasERkVlHShR61ZM9paPsd4OyfoQALpvaI8=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=rvjyhgJmYlIzlaWA7zSO1McTmw4D0MdA/jPxe+Zo/B3/4UyOo2f0BAUX1yDKetAuN\n\t IMnJZfs7uzopulWDUvFyjQgRw7CpH1QNpYC9QoIF6xwdsZM65EzhwVo5ffK62BCNY7\n\t kAxasTNJi0BrvRG7PZTq+ScKK0LoBuCxg0W5qzo/M7+kVcOKxHHeT6YS6PJsD+2cfI\n\t uQhjwDoitNT5xfw93o6ex7LhGu2fO7pHzkM1m5f00NxPpONqs3+lKrhcgKN0LW3n+q\n\t 7+E2I4lm3WLUvt9wkVz3Q/nLZX1QpV68lZLmsqg8mDamIDesAf5luRDF+07aQEZNPD\n\t jErVuSM6pr8GA==", "From": "Radu Sabau via B4 Relay <devnull+radu.sabau.analog.com@kernel.org>", "Date": "Thu, 09 Apr 2026 18:28:27 +0300", "Subject": "[PATCH v7 6/6] docs: iio: adc: ad4691: add driver documentation", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "\n <20260409-ad4692-multichannel-sar-adc-driver-v7-6-be375d4df2c5@analog.com>", "References": "\n <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com>", "In-Reply-To": "\n <20260409-ad4692-multichannel-sar-adc-driver-v7-0-be375d4df2c5@analog.com>", "To": "Lars-Peter Clausen <lars@metafoo.de>,\n Michael Hennerich <Michael.Hennerich@analog.com>,\n Jonathan Cameron <jic23@kernel.org>, David Lechner <dlechner@baylibre.com>,\n\t=?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>,\n Linus Walleij <linusw@kernel.org>, Bartosz Golaszewski <brgl@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>, Jonathan Corbet <corbet@lwn.net>,\n Shuah Khan <skhan@linuxfoundation.org>", "Cc": "linux-iio@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,\n linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,\n Radu Sabau <radu.sabau@analog.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775748505; l=13101;\n i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id;\n bh=IptN2OXLuNKyo/j556/GPrsAWPRNvypfZxc/oV4K/08=;\n b=yxWNyMKAMFayikY2a8aPmPC4cimWIh1kYwt4nLnqEZ9DNF8VoWaaJarr5ZW6UCY0He4TzRChQ\n WrEhManA9QIBRGiv61DldWe7xEDDPeSa9eLlyz8yQ+vSnm6CaUtcPGM", "X-Developer-Key": "i=radu.sabau@analog.com; a=ed25519;\n pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU=", "X-Endpoint-Received": "by B4 Relay for radu.sabau@analog.com/20260220 with\n auth_id=642", "X-Original-From": "Radu Sabau <radu.sabau@analog.com>", "Reply-To": "radu.sabau@analog.com" }, "content": "From: Radu Sabau <radu.sabau@analog.com>\n\nAdd RST documentation for the AD4691 family ADC driver covering\nsupported devices, IIO channels, operating modes, oversampling,\nreference voltage, LDO supply, reset, GP pins, SPI offload support,\nand buffer data format.\n\nSigned-off-by: Radu Sabau <radu.sabau@analog.com>\n---\n Documentation/iio/ad4691.rst | 283 +++++++++++++++++++++++++++++++++++++++++++\n Documentation/iio/index.rst | 1 +\n MAINTAINERS | 1 +\n 3 files changed, 285 insertions(+)", "diff": "diff --git a/Documentation/iio/ad4691.rst b/Documentation/iio/ad4691.rst\nnew file mode 100644\nindex 000000000000..a1012c8b78a3\n--- /dev/null\n+++ b/Documentation/iio/ad4691.rst\n@@ -0,0 +1,283 @@\n+.. SPDX-License-Identifier: GPL-2.0-only\n+\n+=============\n+AD4691 driver\n+=============\n+\n+ADC driver for Analog Devices Inc. AD4691 family of multichannel SAR ADCs.\n+The module name is ``ad4691``.\n+\n+\n+Supported devices\n+=================\n+\n+The following chips are supported by this driver:\n+\n+* `AD4691 <https://www.analog.com/en/products/ad4691.html>`_ — 16-channel, 500 kSPS\n+* `AD4692 <https://www.analog.com/en/products/ad4692.html>`_ — 16-channel, 1 MSPS\n+* `AD4693 <https://www.analog.com/en/products/ad4693.html>`_ — 8-channel, 500 kSPS\n+* `AD4694 <https://www.analog.com/en/products/ad4694.html>`_ — 8-channel, 1 MSPS\n+\n+\n+IIO channels\n+============\n+\n+Each physical ADC input maps to one IIO voltage channel. The AD4691 and AD4692\n+expose 16 channels (``voltage0`` through ``voltage15``); the AD4693 and AD4694\n+expose 8 channels (``voltage0`` through ``voltage7``).\n+\n+All channels share a common scale (``in_voltage_scale``), derived from the\n+reference voltage. Each channel independently exposes:\n+\n+* ``in_voltageN_raw`` — single-shot ADC result\n+* ``in_voltageN_sampling_frequency`` — per-channel effective conversion rate.\n+ In CNV Burst Mode this equals the internal oscillator frequency divided by\n+ the channel's oversampling ratio. In Manual Mode (where oversampling is not\n+ supported) it equals the oscillator frequency directly.\n+* ``in_voltageN_sampling_frequency_available`` — list of valid oscillator\n+ frequencies\n+\n+The following attributes are only available in CNV Burst Mode:\n+\n+* ``in_voltageN_oversampling_ratio`` — per-channel hardware accumulation depth\n+* ``in_voltageN_oversampling_ratio_available`` — list of valid ratios: 1, 2, 4,\n+ 8, 16, 32\n+\n+\n+Operating modes\n+===============\n+\n+The driver supports two operating modes, auto-detected from the device tree at\n+probe time. Both modes transition to and from an internal Autonomous Mode idle\n+state when the IIO buffer is enabled and disabled.\n+\n+Manual Mode\n+-----------\n+\n+Selected when no ``pwms`` property is present in the device tree. The CNV pin\n+is tied to the SPI chip-select: every CS assertion both triggers a new\n+conversion and returns the result of the previous one (pipelined N+1 scheme).\n+\n+To read N channels the driver issues N+1 SPI transfers in a single optimised\n+message:\n+\n+* Transfers 0 to N-1 each carry ``AD4691_ADC_CHAN(n)`` in the TX byte to\n+ select the next channel; the RX byte of transfer ``k+1`` contains the result\n+ of the channel selected in transfer ``k``.\n+* Transfer N is a NOOP (0x00) to flush the last conversion result out of the\n+ pipeline.\n+\n+A user-defined IIO trigger (e.g. hrtimer trigger) drives the trigger handler,\n+which executes the pre-built SPI message and pushes the scan to the buffer.\n+\n+Oversampling is not supported in Manual Mode.\n+\n+CNV Burst Mode\n+--------------\n+\n+Selected when a ``pwms`` property is present in the device tree. The PWM drives\n+the CNV pin independently of SPI at the configured conversion rate, and a GP\n+pin (identified by ``interrupt-names``) asserts DATA_READY at end-of-burst to\n+signal that the AVG_IN result registers are ready to be read.\n+\n+The IRQ handler fires the IIO trigger without stopping the PWM, then disables\n+itself to prevent a second DATA_READY assertion while the trigger handler is\n+running. The trigger handler reads all active ``AVG_IN(n)`` registers in a\n+single optimised SPI message, pushes the scan to the buffer, and re-enables\n+the IRQ.\n+\n+The buffer sampling frequency (i.e. the PWM rate) is controlled by the\n+``sampling_frequency`` attribute on the IIO buffer. Valid values span from the\n+chip's minimum oscillator rate up to its maximum conversion rate (500 kSPS for\n+AD4691/AD4693, 1 MSPS for AD4692/AD4694). In practice, without SPI offload,\n+the SPI read overhead between DATA_READY and the start of the next PWM period\n+limits the achievable rate; the PWM frequency should be set low enough to\n+accommodate the SPI transfer time.\n+\n+Autonomous Mode (idle / single-shot)\n+-------------------------------------\n+\n+The chip idles in Autonomous Mode whenever the IIO buffer is disabled. In this\n+state, ``read_raw`` requests (``in_voltageN_raw``) use the internal oscillator\n+to perform a single conversion on the requested channel and read back the\n+result from the ``AVG_IN(N)`` register. The oscillator is started and stopped\n+for each read to save power.\n+\n+\n+Oversampling\n+============\n+\n+In CNV Burst Mode each channel has an independent hardware accumulator\n+(ACC_DEPTH_IN) that averages a configurable number of successive conversions\n+before DATA_READY asserts. The result is always returned as a 16-bit mean from\n+the ``AVG_IN`` register, so the IIO ``realbits`` and ``storagebits`` are\n+unaffected by the oversampling ratio.\n+\n+Valid ratios are 1, 2, 4, 8, 16 and 32. The default is 1 (no averaging).\n+Oversampling is not supported in Manual Mode.\n+\n+.. code-block:: bash\n+\n+ # Set oversampling ratio to 16 on channel 0\n+ echo 16 > /sys/bus/iio/devices/iio:device0/in_voltage0_oversampling_ratio\n+\n+When OSR > 1 the effective conversion rate reported by\n+``in_voltageN_sampling_frequency`` and used for ``read_raw`` is reduced\n+accordingly, since each output sample requires OSR successive conversions.\n+\n+\n+Reference voltage\n+=================\n+\n+The driver supports two reference configurations, mutually exclusive:\n+\n+* **External reference** (``ref-supply``): a voltage between 2.4 V and 5.25 V\n+ supplied externally. The internal reference buffer is disabled.\n+* **Buffered internal reference** (``refin-supply``): An internal reference\n+ buffer is used. The driver enables ``REFBUF_EN`` in the REF_CTRL register\n+ when this supply is used.\n+\n+Exactly one of ``ref-supply`` or ``refin-supply`` must be present in the\n+device tree.\n+\n+The reference voltage determines the full-scale range:\n+\n+.. code-block::\n+\n+ full-scale = Vref / 2^16 (per LSB)\n+\n+\n+LDO supply\n+==========\n+\n+The chip contains an internal LDO that powers part of the analog front-end.\n+The LDO input can be driven externally via the ``ldo-in-supply`` regulator. If\n+that supply is absent, the driver enables the internal LDO path (``LDO_EN``\n+bit in DEVICE_SETUP).\n+\n+\n+Reset\n+=====\n+\n+The driver supports two reset mechanisms:\n+\n+* **Hardware reset** (``reset-gpios`` in device tree): the GPIO is already\n+ asserted at driver probe by the reset controller framework. The driver waits\n+ for the required 300 µs reset pulse width and then deasserts.\n+* **Software reset** (fallback when ``reset-gpios`` is absent): the driver\n+ writes the software-reset pattern to the SPI_CONFIG_A register.\n+\n+\n+GP pins and interrupts\n+======================\n+\n+The chip exposes up to four general-purpose (GP) pins that can be configured as\n+interrupt or trigger-source outputs. In CNV Burst Mode (non-offload), one GP\n+pin must be wired to an interrupt-capable SoC input and declared in the device\n+tree using the ``interrupts`` and ``interrupt-names`` properties.\n+\n+The ``interrupt-names`` value identifies which GP pin is used (``\"gp0\"``\n+through ``\"gp3\"``). The driver configures that pin as a DATA_READY output in\n+the GPIO_MODE register.\n+\n+Example device tree fragment::\n+\n+ adc@0 {\n+ compatible = \"adi,ad4692\";\n+ ...\n+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-parent = <&gpio0>;\n+ interrupt-names = \"gp0\";\n+ };\n+\n+\n+SPI offload support\n+===================\n+\n+When a SPI offload engine (e.g. the AXI SPI Engine) is present, the driver\n+uses DMA-backed transfers for CPU-independent, high-throughput data capture.\n+SPI offload is detected automatically at probe via ``devm_spi_offload_get()``;\n+if no offload hardware is available the driver falls back to the software\n+triggered-buffer path.\n+\n+Two SPI offload sub-modes exist, corresponding to the two operating modes:\n+\n+CNV Burst offload\n+-----------------\n+\n+Used when a ``pwms`` property is present and SPI offload is available.\n+\n+The PWM drives CNV at the configured rate. On DATA_READY the SPI offload\n+engine automatically executes a pre-built message that reads all active\n+``AVG_IN`` registers and streams the data directly to an IIO DMA buffer with\n+no CPU involvement. A final state-reset transfer re-arms DATA_READY for the\n+next burst.\n+\n+The GP pin used as DATA_READY trigger is supplied by the trigger-source\n+consumer (via ``#trigger-source-cells``) at buffer enable time; no\n+``interrupt-names`` entry is required in this path.\n+\n+The buffer sampling frequency is controlled by the ``sampling_frequency``\n+attribute on the IIO buffer (same as the non-offload CNV Burst path).\n+\n+Manual offload\n+--------------\n+\n+Used when no ``pwms`` property is present and SPI offload is available.\n+\n+A periodic SPI offload trigger controls the conversion rate. On each trigger\n+period, the SPI engine executes an N+1 transfer message (same pipelined scheme\n+as software Manual Mode) and streams the 16-bit ADC results directly to the\n+IIO DMA buffer. Each transfer sends a 16-bit TX word (channel command byte in\n+the upper byte, zero in the lower byte); the chip returns the 16-bit ADC\n+result on MISO. The first transfer's RX is discarded (pipeline flush); results\n+from transfers 1 through N are streamed to the DMA buffer.\n+\n+The ``sampling_frequency`` attribute on the IIO buffer controls the trigger\n+rate (in Hz). The initial rate is 100 kHz — a conservative default chosen\n+because the N+1 SPI transfer overhead in this mode limits the achievable rate\n+relative to the chip's maximum conversion rate.\n+\n+Oversampling is not supported in Manual Mode.\n+\n+\n+Buffer data format\n+==================\n+\n+The IIO buffer data format (``in_voltageN_type``) is the same across all\n+paths: 16-bit unsigned big-endian samples with no shift.\n+\n++-------------------------+-------------+----------+-------+\n+| Path | storagebits | realbits | shift |\n++=========================+=============+==========+=======+\n+| Triggered buffer | 16 | 16 | 0 |\n++-------------------------+-------------+----------+-------+\n+| CNV Burst offload (DMA) | 16 | 16 | 0 |\n++-------------------------+-------------+----------+-------+\n+| Manual offload (DMA) | 16 | 16 | 0 |\n++-------------------------+-------------+----------+-------+\n+\n+In the triggered-buffer path the SPI rx_buf for each transfer points directly\n+into the scan buffer, so the 16-bit big-endian result is written in place with\n+no additional copying.\n+\n+In the DMA offload paths the SPI offload engine streams 16-bit words (one per\n+active channel) directly into the IIO DMA buffer:\n+\n+* **CNV Burst offload**: each channel read uses a 16-bit address phase followed\n+ by a 16-bit data phase; only the data phase is flagged for DMA streaming, so\n+ the 16-bit result lands directly in the buffer.\n+* **Manual offload**: each 16-bit SPI transfer carries the channel command on\n+ TX and receives the 16-bit ADC result on RX; results are streamed to the\n+ DMA buffer one 16-bit word per channel.\n+\n+The ``in_voltageN_type`` sysfs attribute reflects the active scan type.\n+\n+\n+Unimplemented features\n+======================\n+\n+* GPIO controller functionality of the GP pins\n+* Clamp status and overrange events\n+* Raw accumulator (ACC_IN) and accumulator status registers\n+* ADC_BUSY and overrun status interrupts\ndiff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst\nindex ba3e609c6a13..007e0a1fcc5a 100644\n--- a/Documentation/iio/index.rst\n+++ b/Documentation/iio/index.rst\n@@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers\n ad4000\n ad4030\n ad4062\n+ ad4691\n ad4695\n ad7191\n ad7380\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex 24e4502b8292..819d8b6eb6bb 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1491,6 +1491,7 @@ S:\tSupported\n W:\thttps://ez.analog.com/linux-software-drivers\n F:\tDocumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml\n F:\tdrivers/iio/adc/ad4691.c\n+F:\tdrivers/iio/adc/ad4691.rst\n \n ANALOG DEVICES INC AD4695 DRIVER\n M:\tMichael Hennerich <michael.hennerich@analog.com>\n", "prefixes": [ "v7", "6/6" ] }