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GET /api/1.2/patches/2221484/?format=api
{ "id": 2221484, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260409133651.92580-1-ankita@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260409133651.92580-1-ankita@nvidia.com>", "list_archive_url": null, "date": "2026-04-09T13:36:51", "name": "[v2,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7602e1bb08356e57b66e53cc7e7a98050a4a609a", "submitter": { "id": 86155, "url": "http://patchwork.ozlabs.org/api/1.2/people/86155/?format=api", "name": "Ankit Agrawal", "email": "ankita@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260409133651.92580-1-ankita@nvidia.com/mbox/", "series": [ { "id": 499305, "url": "http://patchwork.ozlabs.org/api/1.2/series/499305/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499305", "date": "2026-04-09T13:36:51", "name": "[v2,1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499305/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221484/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221484/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52214-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=hS1a+9hD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Ankit Agrawal <ankita@nvidia.com>", "To": "<alex@shazbot.org>", "CC": "<kvm@vger.kernel.org>, <jgg@ziepe.ca>, <yishaih@nvidia.com>,\n\t<skolothumtho@nvidia.com>, <kevin.tian@intel.com>, <ankita@nvidia.com>,\n\t<bhelgaas@google.com>, <linux-kernel@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>", "Subject": "[PATCH v2 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness\n check via CXL DVSEC", "Date": "Thu, 9 Apr 2026 13:36:51 +0000", "Message-ID": "<20260409133651.92580-1-ankita@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00029929:EE_|DS0PR12MB6413:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5a186f2e-dd3c-4c5e-25f6-08de963d1966", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\t0indadCnXRpxZQ2I2B5XP3mw9EADehAPzxCxzmX17kiKWMjzAaDPG9JpFDXDoUHESO4ucKRY6Y96eIsV+51b8ZaX0km9vPFPd0O6MGr/Lfm2VnEAm1J7odCs30lQpinRYJh876Qag/2qH7zimSTwruJb9xwK2fQ1mNe+wWqjHuXzOlklQHs1Jr4ic6OAxI3oX2NY71bAjPfNxNMw7rrYhan1pTO5Jh0Pr43kIEKtTdaX2aoAeyve5v9P5Sj/0LZ2//UZZqJ3d7lR4ACrTuDC1Hx2vXJTs2+wC8dYp3k+l/swdpcF41ywK1/7ymhXkPTWsBMxlHpf3Xj3NVgIGAJ90o6Xkq+v0d5MH4rK1jBSEvUgoMuwnHXE7A+k3hodmwpM3Tw3g7e8MFRmBeSepKxvyjuI4Y4oAf07hKKSc6dkmU1VaWpNLCqR4+Jj/t8vmDSZX1CKyGuzQpDAwAsKurKyPpdX7HTPkbXmyq3hgEHwvpaH/y6VG5StRBYFIo6MqGv6JcP+Dmygi8QXzNIhyIIVMBmO7zWDRkJYH3LY2i5dVAZUb6FqVMcYOKvYu4W3fy4o/9INquKIAqEIyviO17+9V441c0gM37OoIEjebEIX5uTrHUEgH6/ay7YW005BlBV07M7H2EWDae6Z6nhjbkC4ZW9javgx45Y0+pyApDFIvU/NsB7BDrv9e8EtK17T51TmtdkHkHMJDYgmc4p8vXpJC1e0+TLtAYUEUnPigiXsE2gD7L7nAizIWvy6DVMvUS7wyviNWgenFf1p+h62aRvAtQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t3VT97SbBXssT5YYQ2UZJFJUEPRjl+5iIG66pN1QxCQ93s/IsPIcq57qwWfTMSxMyuC1e/0R8A+rCCzCuILox8PAqlHi9xgxnHsZY08AsW0AnznpYPOpCdT4PAUnL5zVctAj/KMqsAE5RoZuoO/h2JOL0vDBNUekhBt2P0htMHhCfzQn+B7kkR0muD/JvlcmqUSjjTNRc082TtlZ9YzWKFrdxULwEYTEsNEiuyVbvfDVWWJhJ49iif/ti8q/qn40F0Hzuk7974TyP0lngUahHdObtplzr8D0yct7CCN2BXU9QJBT4lDATx2iZ/2uM/jMADVhSw8GFOgkyx/y506/9Fc+n+R7+6ZNTpCS4/E3ekFfgyFZcCdN71MdmgUW4r6iTZLfGn39+9uA+UH8xuV0blyPVJSR9g3r644vO0lte1DpYzhhUaWxeeCiKfDxHl1vV", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Apr 2026 13:37:09.4626\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5a186f2e-dd3c-4c5e-25f6-08de963d1966", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF00029929.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB6413" }, "content": "Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside\nthe existing legacy BAR0 polling path. On probe and after reset, the\ndriver reads the CXL Device DVSEC capability to determine whether the\nGPU memory is valid. This is checked by polling on the Memory_Active bit\nbased on the Memory_Active_Timeout.\n\nA static inline wrapper dispatches to the appropriate readiness check\nbased on whether the CXL DVSEC capability is present.\n\nSuggested-by: Alex Williamson <alex@shazbot.org>\nSigned-off-by: Ankit Agrawal <ankita@nvidia.com>\n---\n drivers/vfio/pci/nvgrace-gpu/main.c | 75 ++++++++++++++++++++++++++---\n include/uapi/linux/pci_regs.h | 1 +\n 2 files changed, 68 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c\nindex fa056b69f899..52f7e3a3054a 100644\n--- a/drivers/vfio/pci/nvgrace-gpu/main.c\n+++ b/drivers/vfio/pci/nvgrace-gpu/main.c\n@@ -64,6 +64,8 @@ struct nvgrace_gpu_pci_core_device {\n \tbool has_mig_hw_bug;\n \t/* GPU has just been reset */\n \tbool reset_done;\n+\t/* CXL Device DVSEC offset; 0 if not present (legacy GB path) */\n+\tint cxl_dvsec;\n };\n \n static void nvgrace_gpu_init_fake_bar_emu_regs(struct vfio_device *core_vdev)\n@@ -242,7 +244,7 @@ static void nvgrace_gpu_close_device(struct vfio_device *core_vdev)\n \tvfio_pci_core_close_device(core_vdev);\n }\n \n-static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n+static int nvgrace_gpu_wait_device_ready_legacy(void __iomem *io)\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(POLL_TIMEOUT_MS);\n \n@@ -256,6 +258,59 @@ static int nvgrace_gpu_wait_device_ready(void __iomem *io)\n \treturn -ETIME;\n }\n \n+/*\n+ * Decode the 3-bit Memory_Active_Timeout field from CXL DVSEC Range 1 Low\n+ * (bits 15:13) into milliseconds. Encoding per CXL spec r4.0 sec 8.1.3.8.2:\n+ * 000b = 1s, 001b = 4s, 010b = 16s, 011b = 64s, 100b = 256s,\n+ * 101b-111b = reserved (clamped to 256s).\n+ */\n+static inline unsigned long nvgrace_gpu_cxl_mem_active_timeout_ms(u8 timeout)\n+{\n+\treturn 1000UL << (2 * min_t(u8, timeout, 4));\n+}\n+\n+static int nvgrace_gpu_wait_device_ready_bw_next(struct nvgrace_gpu_pci_core_device *nvdev)\n+{\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n+\tint pcie_dvsec = nvdev->cxl_dvsec;\n+\tunsigned long timeout;\n+\tu32 dvsec_memory_status;\n+\tu8 mem_active_timeout;\n+\n+\tpci_read_config_dword(pdev, pcie_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n+\t\t\t &dvsec_memory_status);\n+\n+\tif (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID))\n+\t\treturn -ENODEV;\n+\n+\tmem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,\n+\t\t\t\t dvsec_memory_status);\n+\n+\ttimeout = jiffies +\n+\t\t msecs_to_jiffies(nvgrace_gpu_cxl_mem_active_timeout_ms(mem_active_timeout));\n+\n+\tdo {\n+\t\tpci_read_config_dword(pdev,\n+\t\t\t\t pcie_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),\n+\t\t\t\t &dvsec_memory_status);\n+\n+\t\tif (dvsec_memory_status & PCI_DVSEC_CXL_MEM_ACTIVE)\n+\t\t\treturn 0;\n+\n+\t\tmsleep(POLL_QUANTUM_MS);\n+\t} while (!time_after(jiffies, timeout));\n+\n+\treturn -ETIME;\n+}\n+\n+static inline int nvgrace_gpu_wait_device_ready(struct nvgrace_gpu_pci_core_device *nvdev,\n+\t\t\t\t\t\tvoid __iomem *io)\n+{\n+\treturn nvdev->cxl_dvsec ?\n+\t\tnvgrace_gpu_wait_device_ready_bw_next(nvdev) :\n+\t\tnvgrace_gpu_wait_device_ready_legacy(io);\n+}\n+\n /*\n * If the GPU memory is accessed by the CPU while the GPU is not ready\n * after reset, it can cause harmless corrected RAS events to be logged.\n@@ -275,7 +330,7 @@ nvgrace_gpu_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n \tif (!__vfio_pci_memory_enabled(vdev))\n \t\treturn -EIO;\n \n-\tret = nvgrace_gpu_wait_device_ready(vdev->barmap[0]);\n+\tret = nvgrace_gpu_wait_device_ready(nvdev, vdev->barmap[0]);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1146,8 +1201,9 @@ static bool nvgrace_gpu_has_mig_hw_bug(struct pci_dev *pdev)\n * Ensure that the BAR0 region is enabled before accessing the\n * registers.\n */\n-static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n+static int nvgrace_gpu_probe_check_device_ready(struct nvgrace_gpu_pci_core_device *nvdev)\n {\n+\tstruct pci_dev *pdev = nvdev->core_device.pdev;\n \tvoid __iomem *io;\n \tint ret;\n \n@@ -1165,7 +1221,7 @@ static int nvgrace_gpu_probe_check_device_ready(struct pci_dev *pdev)\n \t\tgoto iomap_exit;\n \t}\n \n-\tret = nvgrace_gpu_wait_device_ready(io);\n+\tret = nvgrace_gpu_wait_device_ready(nvdev, io);\n \n \tpci_iounmap(pdev, io);\n iomap_exit:\n@@ -1183,10 +1239,6 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \tu64 memphys, memlength;\n \tint ret;\n \n-\tret = nvgrace_gpu_probe_check_device_ready(pdev);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = nvgrace_gpu_fetch_memory_property(pdev, &memphys, &memlength);\n \tif (!ret)\n \t\tops = &nvgrace_gpu_pci_ops;\n@@ -1198,6 +1250,13 @@ static int nvgrace_gpu_probe(struct pci_dev *pdev,\n \n \tdev_set_drvdata(&pdev->dev, &nvdev->core_device);\n \n+\tnvdev->cxl_dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t\t PCI_DVSEC_CXL_DEVICE);\n+\n+\tret = nvgrace_gpu_probe_check_device_ready(nvdev);\n+\tif (ret)\n+\t\tgoto out_put_vdev;\n+\n \tif (ops == &nvgrace_gpu_pci_ops) {\n \t\tnvdev->has_mig_hw_bug = nvgrace_gpu_has_mig_hw_bug(pdev);\n \ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350..718fb630f5bb 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1357,6 +1357,7 @@\n #define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i)\t\t(0x1C + (i * 0x10))\n #define PCI_DVSEC_CXL_MEM_INFO_VALID\t\t\t_BITUL(0)\n #define PCI_DVSEC_CXL_MEM_ACTIVE\t\t\t_BITUL(1)\n+#define PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT\t\t__GENMASK(15, 13)\n #define PCI_DVSEC_CXL_MEM_SIZE_LOW\t\t\t__GENMASK(31, 28)\n #define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i)\t\t(0x20 + (i * 0x10))\n #define PCI_DVSEC_CXL_RANGE_BASE_LOW(i)\t\t(0x24 + (i * 0x10))\n", "prefixes": [ "v2", "1/1" ] }