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{
    "id": 2221432,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221432/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260409131340.168556-4-pshete@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260409131340.168556-4-pshete@nvidia.com>",
    "list_archive_url": null,
    "date": "2026-04-09T13:13:37",
    "name": "[3/6] pinctrl: tegra: Add Tegra238 pinmux driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "4b836d42ea90610ed63f0635d973e6859f1ca1e9",
    "submitter": {
        "id": 82424,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/82424/?format=api",
        "name": "Prathamesh Shete",
        "email": "pshete@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260409131340.168556-4-pshete@nvidia.com/mbox/",
    "series": [
        {
            "id": 499291,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/499291/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=499291",
            "date": "2026-04-09T13:13:34",
            "name": "Add Tegra238 and Tegra264 pinctrl support",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/499291/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2221432/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2221432/checks/",
    "tags": {},
    "related": [],
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        "From": "<pshete@nvidia.com>",
        "To": "<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<arnd@arndb.de>, <bjorn.andersson@oss.qualcomm.com>, <conor+dt@kernel.org>,\n\t<dmitry.baryshkov@oss.qualcomm.com>, <ebiggers@kernel.org>,\n\t<geert@linux-m68k.org>, <jonathanh@nvidia.com>, <krzk+dt@kernel.org>,\n\t<kuninori.morimoto.gx@renesas.com>, <linusw@kernel.org>,\n\t<luca.weiss@fairphone.com>, <michal.simek@amd.com>,\n\t<prabhakar.mahadev-lad.rj@bp.renesas.com>, <robh@kernel.org>,\n\t<rosenp@gmail.com>, <sven@kernel.org>, <thierry.reding@kernel.org>,\n\t<webgeek1234@gmail.com>",
        "CC": "<pshete@nvidia.com>",
        "Subject": "[PATCH 3/6] pinctrl: tegra: Add Tegra238 pinmux driver",
        "Date": "Thu, 9 Apr 2026 13:13:37 +0000",
        "Message-ID": "<20260409131340.168556-4-pshete@nvidia.com>",
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    "content": "From: Prathamesh Shete <pshete@nvidia.com>\n\nThis change adds support for the two pin controllers\n(MAIN and AON) found on Tegra238.\n\nSigned-off-by: Prathamesh Shete <pshete@nvidia.com>\n---\n drivers/pinctrl/tegra/Kconfig            |    9 +\n drivers/pinctrl/tegra/Makefile           |    1 +\n drivers/pinctrl/tegra/pinctrl-tegra238.c | 2056 ++++++++++++++++++++++\n 3 files changed, 2066 insertions(+)\n create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c",
    "diff": "diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig\nindex 660d101ea367..ccb8c337b4ee 100644\n--- a/drivers/pinctrl/tegra/Kconfig\n+++ b/drivers/pinctrl/tegra/Kconfig\n@@ -36,6 +36,15 @@ config PINCTRL_TEGRA234\n \tbool\n \tselect PINCTRL_TEGRA\n \n+config PINCTRL_TEGRA238\n+\ttristate \"NVIDIA Tegra238 pinctrl driver\"\n+\tselect PINCTRL_TEGRA\n+\thelp\n+\t  Say Y or M here to enable support for the pinctrl driver for\n+\t  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing\n+\t  and configuration for the MAIN and AON pin controllers found\n+\t  on Tegra238.\n+\n config PINCTRL_TEGRA_XUSB\n \tdef_bool y if ARCH_TEGRA\n \tselect GENERIC_PHY\ndiff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile\nindex 82176526549e..ce700bbcbf6e 100644\n--- a/drivers/pinctrl/tegra/Makefile\n+++ b/drivers/pinctrl/tegra/Makefile\n@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_TEGRA210)\t\t+= pinctrl-tegra210.o\n obj-$(CONFIG_PINCTRL_TEGRA186)\t\t+= pinctrl-tegra186.o\n obj-$(CONFIG_PINCTRL_TEGRA194)\t\t+= pinctrl-tegra194.o\n obj-$(CONFIG_PINCTRL_TEGRA234)\t\t+= pinctrl-tegra234.o\n+obj-$(CONFIG_PINCTRL_TEGRA238)\t\t+= pinctrl-tegra238.o\n obj-$(CONFIG_PINCTRL_TEGRA_XUSB)\t+= pinctrl-tegra-xusb.o\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra238.c b/drivers/pinctrl/tegra/pinctrl-tegra238.c\nnew file mode 100644\nindex 000000000000..421da334151c\n--- /dev/null\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra238.c\n@@ -0,0 +1,2056 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Pinctrl data for the NVIDIA Tegra238 pinmux\n+ *\n+ * Copyright (c) 2022-2026, NVIDIA CORPORATION.  All rights reserved.\n+ */\n+\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+#include <linux/pinctrl/pinctrl.h>\n+#include <linux/pinctrl/pinmux.h>\n+\n+#include \"pinctrl-tegra.h\"\n+\n+/* Define unique ID for each pins */\n+enum {\n+\tTEGRA_PIN_GPU_PWR_REQ_PA0,\n+\tTEGRA_PIN_GP_PWM5_PA1,\n+\tTEGRA_PIN_GP_PWM6_PA2,\n+\tTEGRA_PIN_SPI3_SCK_PA3,\n+\tTEGRA_PIN_SPI3_MISO_PA4,\n+\tTEGRA_PIN_SPI3_MOSI_PA5,\n+\tTEGRA_PIN_SPI3_CS0_PA6,\n+\tTEGRA_PIN_SPI3_CS1_PA7,\n+\tTEGRA_PIN_SPI1_SCK_PB0,\n+\tTEGRA_PIN_SPI1_MISO_PB1,\n+\tTEGRA_PIN_SPI1_MOSI_PB2,\n+\tTEGRA_PIN_SPI1_CS0_PB3,\n+\tTEGRA_PIN_SPI1_CS1_PB4,\n+\tTEGRA_PIN_PWR_I2C_SCL_PC0,\n+\tTEGRA_PIN_PWR_I2C_SDA_PC1,\n+\tTEGRA_PIN_EXTPERIPH1_CLK_PC2,\n+\tTEGRA_PIN_EXTPERIPH2_CLK_PC3,\n+\tTEGRA_PIN_CAM_I2C_SCL_PC4,\n+\tTEGRA_PIN_CAM_I2C_SDA_PC5,\n+\tTEGRA_PIN_SOC_GPIO23_PC6,\n+\tTEGRA_PIN_SOC_GPIO24_PC7,\n+\tTEGRA_PIN_SOC_GPIO27_PD0,\n+\tTEGRA_PIN_SOC_GPIO55_PD1,\n+\tTEGRA_PIN_SOC_GPIO29_PD2,\n+\tTEGRA_PIN_SOC_GPIO33_PD3,\n+\tTEGRA_PIN_SOC_GPIO32_PD4,\n+\tTEGRA_PIN_SOC_GPIO35_PD5,\n+\tTEGRA_PIN_SOC_GPIO37_PD6,\n+\tTEGRA_PIN_SOC_GPIO56_PD7,\n+\tTEGRA_PIN_UART1_TX_PE0,\n+\tTEGRA_PIN_UART1_RX_PE1,\n+\tTEGRA_PIN_UART1_RTS_PE2,\n+\tTEGRA_PIN_UART1_CTS_PE3,\n+\tTEGRA_PIN_SOC_GPIO13_PF0,\n+\tTEGRA_PIN_SOC_GPIO14_PF1,\n+\tTEGRA_PIN_SOC_GPIO15_PF2,\n+\tTEGRA_PIN_SOC_GPIO16_PF3,\n+\tTEGRA_PIN_SOC_GPIO17_PF4,\n+\tTEGRA_PIN_SOC_GPIO18_PF5,\n+\tTEGRA_PIN_SOC_GPIO20_PF6,\n+\tTEGRA_PIN_SOC_GPIO21_PF7,\n+\tTEGRA_PIN_SOC_GPIO22_PG0,\n+\tTEGRA_PIN_SOC_GPIO06_PG1,\n+\tTEGRA_PIN_UART4_TX_PG2,\n+\tTEGRA_PIN_UART4_RX_PG3,\n+\tTEGRA_PIN_UART4_RTS_PG4,\n+\tTEGRA_PIN_UART4_CTS_PG5,\n+\tTEGRA_PIN_SOC_GPIO41_PG6,\n+\tTEGRA_PIN_SOC_GPIO42_PG7,\n+\tTEGRA_PIN_SOC_GPIO43_PH0,\n+\tTEGRA_PIN_SOC_GPIO44_PH1,\n+\tTEGRA_PIN_GEN1_I2C_SCL_PH2,\n+\tTEGRA_PIN_GEN1_I2C_SDA_PH3,\n+\tTEGRA_PIN_CPU_PWR_REQ_PH4,\n+\tTEGRA_PIN_SOC_GPIO07_PH5,\n+\tTEGRA_PIN_DAP3_CLK_PJ0,\n+\tTEGRA_PIN_DAP3_DOUT_PJ1,\n+\tTEGRA_PIN_DAP3_DIN_PJ2,\n+\tTEGRA_PIN_DAP3_FS_PJ3,\n+\tTEGRA_PIN_SOC_GPIO57_PJ4,\n+\tTEGRA_PIN_SOC_GPIO58_PJ5,\n+\tTEGRA_PIN_SOC_GPIO59_PJ6,\n+\tTEGRA_PIN_SOC_GPIO60_PJ7,\n+\tTEGRA_PIN_SOC_GPIO45_PK0,\n+\tTEGRA_PIN_SOC_GPIO46_PK1,\n+\tTEGRA_PIN_SOC_GPIO47_PK2,\n+\tTEGRA_PIN_SOC_GPIO48_PK3,\n+\tTEGRA_PIN_QSPI0_SCK_PL0,\n+\tTEGRA_PIN_QSPI0_IO0_PL1,\n+\tTEGRA_PIN_QSPI0_IO1_PL2,\n+\tTEGRA_PIN_QSPI0_CS_N_PL3,\n+\tTEGRA_PIN_SOC_GPIO152_PL4,\n+\tTEGRA_PIN_SOC_GPIO153_PL5,\n+\tTEGRA_PIN_SOC_GPIO154_PL6,\n+\tTEGRA_PIN_SOC_GPIO155_PL7,\n+\tTEGRA_PIN_SOC_GPIO156_PM0,\n+\tTEGRA_PIN_SOC_GPIO157_PM1,\n+\tTEGRA_PIN_SOC_GPIO158_PM2,\n+\tTEGRA_PIN_SOC_GPIO159_PM3,\n+\tTEGRA_PIN_SOC_GPIO160_PM4,\n+\tTEGRA_PIN_SOC_GPIO161_PM5,\n+\tTEGRA_PIN_SOC_GPIO162_PM6,\n+\tTEGRA_PIN_UART7_TX_PM7,\n+\tTEGRA_PIN_UART7_RX_PN0,\n+\tTEGRA_PIN_UART7_RTS_PN1,\n+\tTEGRA_PIN_UART7_CTS_PN2,\n+\tTEGRA_PIN_SOC_GPIO167_PP0,\n+\tTEGRA_PIN_SOC_GPIO168_PP1,\n+\tTEGRA_PIN_SOC_GPIO169_PP2,\n+\tTEGRA_PIN_SOC_GPIO170_PP3,\n+\tTEGRA_PIN_DAP4_SCLK_PP4,\n+\tTEGRA_PIN_DAP4_DOUT_PP5,\n+\tTEGRA_PIN_DAP4_DIN_PP6,\n+\tTEGRA_PIN_DAP4_FS_PP7,\n+\tTEGRA_PIN_SOC_GPIO171_PQ0,\n+\tTEGRA_PIN_SOC_GPIO172_PQ1,\n+\tTEGRA_PIN_SOC_GPIO173_PQ2,\n+\tTEGRA_PIN_SOC_GPIO61_PR0,\n+\tTEGRA_PIN_SOC_GPIO62_PR1,\n+\tTEGRA_PIN_SOC_GPIO63_PR2,\n+\tTEGRA_PIN_SOC_GPIO64_PR3,\n+\tTEGRA_PIN_SOC_GPIO65_PR4,\n+\tTEGRA_PIN_SOC_GPIO66_PR5,\n+\tTEGRA_PIN_SOC_GPIO67_PR6,\n+\tTEGRA_PIN_SOC_GPIO68_PR7,\n+\tTEGRA_PIN_GEN4_I2C_SCL_PS0,\n+\tTEGRA_PIN_GEN4_I2C_SDA_PS1,\n+\tTEGRA_PIN_SOC_GPIO75_PS2,\n+\tTEGRA_PIN_GEN7_I2C_SCL_PS3,\n+\tTEGRA_PIN_GEN7_I2C_SDA_PS4,\n+\tTEGRA_PIN_SOC_GPIO78_PS5,\n+\tTEGRA_PIN_GEN9_I2C_SCL_PS6,\n+\tTEGRA_PIN_GEN9_I2C_SDA_PS7,\n+\tTEGRA_PIN_SOC_GPIO81_PT0,\n+\tTEGRA_PIN_SOC_GPIO36_PT1,\n+\tTEGRA_PIN_SOC_GPIO53_PT2,\n+\tTEGRA_PIN_SOC_GPIO38_PT3,\n+\tTEGRA_PIN_SOC_GPIO40_PT4,\n+\tTEGRA_PIN_SOC_GPIO34_PT5,\n+\tTEGRA_PIN_USB_VBUS_EN0_PT6,\n+\tTEGRA_PIN_USB_VBUS_EN1_PT7,\n+\tTEGRA_PIN_SDMMC1_CLK_PU0,\n+\tTEGRA_PIN_SDMMC1_CMD_PU1,\n+\tTEGRA_PIN_SDMMC1_DAT0_PU2,\n+\tTEGRA_PIN_SDMMC1_DAT1_PU3,\n+\tTEGRA_PIN_SDMMC1_DAT2_PU4,\n+\tTEGRA_PIN_SDMMC1_DAT3_PU5,\n+\tTEGRA_PIN_UFS0_REF_CLK_PV0,\n+\tTEGRA_PIN_UFS0_RST_N_PV1,\n+\tTEGRA_PIN_PEX_L0_CLKREQ_N_PW0,\n+\tTEGRA_PIN_PEX_L0_RST_N_PW1,\n+\tTEGRA_PIN_PEX_L1_CLKREQ_N_PW2,\n+\tTEGRA_PIN_PEX_L1_RST_N_PW3,\n+\tTEGRA_PIN_PEX_L2_CLKREQ_N_PW4,\n+\tTEGRA_PIN_PEX_L2_RST_N_PW5,\n+\tTEGRA_PIN_PEX_L3_CLKREQ_N_PW6,\n+\tTEGRA_PIN_PEX_L3_RST_N_PW7,\n+\tTEGRA_PIN_PEX_WAKE_N_PX0,\n+\tTEGRA_PIN_DP_AUX_CH0_HPD_PX1,\n+\tTEGRA_PIN_SDMMC1_COMP,\n+};\n+\n+enum {\n+\tTEGRA_PIN_BOOTV_CTL_N_PAA0,\n+\tTEGRA_PIN_SOC_GPIO00_PAA1,\n+\tTEGRA_PIN_VCOMP_ALERT_PAA2,\n+\tTEGRA_PIN_PWM1_PAA3,\n+\tTEGRA_PIN_BATT_OC_PAA4,\n+\tTEGRA_PIN_SOC_GPIO04_PAA5,\n+\tTEGRA_PIN_SOC_GPIO25_PAA6,\n+\tTEGRA_PIN_SOC_GPIO26_PAA7,\n+\tTEGRA_PIN_HDMI_CEC_PBB0,\n+\tTEGRA_PIN_SPI2_SCK_PCC0,\n+\tTEGRA_PIN_SPI2_MISO_PCC1,\n+\tTEGRA_PIN_SPI2_MOSI_PCC2,\n+\tTEGRA_PIN_SPI2_CS0_PCC3,\n+\tTEGRA_PIN_SPI2_CS1_PCC4,\n+\tTEGRA_PIN_UART3_TX_PCC5,\n+\tTEGRA_PIN_UART3_RX_PCC6,\n+\tTEGRA_PIN_GEN2_I2C_SCL_PCC7,\n+\tTEGRA_PIN_GEN2_I2C_SDA_PDD0,\n+\tTEGRA_PIN_GEN8_I2C_SCL_PDD1,\n+\tTEGRA_PIN_GEN8_I2C_SDA_PDD2,\n+\tTEGRA_PIN_TOUCH_CLK_PDD3,\n+\tTEGRA_PIN_DMIC1_CLK_PDD4,\n+\tTEGRA_PIN_DMIC1_DAT_PDD5,\n+\tTEGRA_PIN_SOC_GPIO19_PDD6,\n+\tTEGRA_PIN_PWM2_PDD7,\n+\tTEGRA_PIN_PWM3_PEE0,\n+\tTEGRA_PIN_PWM7_PEE1,\n+\tTEGRA_PIN_SOC_GPIO49_PEE2,\n+\tTEGRA_PIN_SOC_GPIO82_PEE3,\n+\tTEGRA_PIN_SOC_GPIO50_PEE4,\n+\tTEGRA_PIN_SOC_GPIO83_PEE5,\n+\tTEGRA_PIN_SOC_GPIO69_PFF0,\n+\tTEGRA_PIN_SOC_GPIO70_PFF1,\n+\tTEGRA_PIN_SOC_GPIO71_PFF2,\n+\tTEGRA_PIN_SOC_GPIO72_PFF3,\n+\tTEGRA_PIN_SOC_GPIO73_PFF4,\n+\tTEGRA_PIN_SOC_GPIO74_PFF5,\n+\tTEGRA_PIN_SOC_GPIO80_PFF6,\n+\tTEGRA_PIN_SOC_GPIO76_PFF7,\n+\tTEGRA_PIN_SOC_GPIO77_PGG0,\n+\tTEGRA_PIN_SOC_GPIO84_PGG1,\n+\tTEGRA_PIN_UART2_TX_PGG2,\n+\tTEGRA_PIN_UART2_RX_PGG3,\n+\tTEGRA_PIN_UART2_RTS_PGG4,\n+\tTEGRA_PIN_UART2_CTS_PGG5,\n+\tTEGRA_PIN_SOC_GPIO85_PGG6,\n+\tTEGRA_PIN_UART5_TX_PGG7,\n+\tTEGRA_PIN_UART5_RX_PHH0,\n+\tTEGRA_PIN_UART5_RTS_PHH1,\n+\tTEGRA_PIN_UART5_CTS_PHH2,\n+\tTEGRA_PIN_SOC_GPIO86_PHH3,\n+};\n+\n+/* Table for pin descriptor */\n+static const struct pinctrl_pin_desc tegra238_pins[] = {\n+\tPINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PA0, \"GPU_PWR_REQ_PA0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GP_PWM5_PA1, \"GP_PWM5_PA1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GP_PWM6_PA2, \"GP_PWM6_PA2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PA3, \"SPI3_SCK_PA3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PA4, \"SPI3_MISO_PA4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PA5, \"SPI3_MOSI_PA5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PA6, \"SPI3_CS0_PA6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PA7, \"SPI3_CS1_PA7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PB0, \"SPI1_SCK_PB0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PB1, \"SPI1_MISO_PB1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PB2, \"SPI1_MOSI_PB2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PB3, \"SPI1_CS0_PB3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PB4, \"SPI1_CS1_PB4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PC0, \"PWR_I2C_SCL_PC0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PC1, \"PWR_I2C_SDA_PC1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PC2, \"EXTPERIPH1_CLK_PC2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PC3, \"EXTPERIPH2_CLK_PC3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PC4, \"CAM_I2C_SCL_PC4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PC5, \"CAM_I2C_SDA_PC5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PC6, \"SOC_GPIO23_PC6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PC7, \"SOC_GPIO24_PC7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PD0, \"SOC_GPIO27_PD0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PD1, \"SOC_GPIO55_PD1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PD2, \"SOC_GPIO29_PD2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PD3, \"SOC_GPIO33_PD3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PD4, \"SOC_GPIO32_PD4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PD5, \"SOC_GPIO35_PD5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PD6, \"SOC_GPIO37_PD6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PD7, \"SOC_GPIO56_PD7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART1_TX_PE0, \"UART1_TX_PE0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART1_RX_PE1, \"UART1_RX_PE1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART1_RTS_PE2, \"UART1_RTS_PE2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART1_CTS_PE3, \"UART1_CTS_PE3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PF0, \"SOC_GPIO13_PF0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PF1, \"SOC_GPIO14_PF1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PF2, \"SOC_GPIO15_PF2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PF3, \"SOC_GPIO16_PF3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PF4, \"SOC_GPIO17_PF4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PF5, \"SOC_GPIO18_PF5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PF6, \"SOC_GPIO20_PF6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PF7, \"SOC_GPIO21_PF7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PG0, \"SOC_GPIO22_PG0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PG1, \"SOC_GPIO06_PG1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_TX_PG2, \"UART4_TX_PG2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_RX_PG3, \"UART4_RX_PG3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_RTS_PG4, \"UART4_RTS_PG4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART4_CTS_PG5, \"UART4_CTS_PG5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PG6, \"SOC_GPIO41_PG6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PG7, \"SOC_GPIO42_PG7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PH0, \"SOC_GPIO43_PH0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PH1, \"SOC_GPIO44_PH1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PH2, \"GEN1_I2C_SCL_PH2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PH3, \"GEN1_I2C_SDA_PH3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH4, \"CPU_PWR_REQ_PH4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PH5, \"SOC_GPIO07_PH5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP3_CLK_PJ0, \"DAP3_CLK_PJ0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PJ1, \"DAP3_DOUT_PJ1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PJ2, \"DAP3_DIN_PJ2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP3_FS_PJ3, \"DAP3_FS_PJ3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PJ4, \"SOC_GPIO57_PJ4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PJ5, \"SOC_GPIO58_PJ5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PJ6, \"SOC_GPIO59_PJ6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PJ7, \"SOC_GPIO60_PJ7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PK0, \"SOC_GPIO45_PK0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PK1, \"SOC_GPIO46_PK1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PK2, \"SOC_GPIO47_PK2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PK3, \"SOC_GPIO48_PK3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PL0, \"QSPI0_SCK_PL0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PL1, \"QSPI0_IO0_PL1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PL2, \"QSPI0_IO1_PL2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PL3, \"QSPI0_CS_N_PL3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PL4, \"SOC_GPIO152_PL4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PL5, \"SOC_GPIO153_PL5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO154_PL6, \"SOC_GPIO154_PL6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PL7, \"SOC_GPIO155_PL7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO156_PM0, \"SOC_GPIO156_PM0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO157_PM1, \"SOC_GPIO157_PM1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO158_PM2, \"SOC_GPIO158_PM2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO159_PM3, \"SOC_GPIO159_PM3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO160_PM4, \"SOC_GPIO160_PM4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO161_PM5, \"SOC_GPIO161_PM5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO162_PM6, \"SOC_GPIO162_PM6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART7_TX_PM7, \"UART7_TX_PM7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART7_RX_PN0, \"UART7_RX_PN0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART7_RTS_PN1, \"UART7_RTS_PN1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART7_CTS_PN2, \"UART7_CTS_PN2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO167_PP0, \"SOC_GPIO167_PP0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO168_PP1, \"SOC_GPIO168_PP1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO169_PP2, \"SOC_GPIO169_PP2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PP3, \"SOC_GPIO170_PP3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP4, \"DAP4_SCLK_PP4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP5, \"DAP4_DOUT_PP5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP6, \"DAP4_DIN_PP6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP7, \"DAP4_FS_PP7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PQ0, \"SOC_GPIO171_PQ0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PQ1, \"SOC_GPIO172_PQ1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PQ2, \"SOC_GPIO173_PQ2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO61_PR0, \"SOC_GPIO61_PR0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO62_PR1, \"SOC_GPIO62_PR1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO63_PR2, \"SOC_GPIO63_PR2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO64_PR3, \"SOC_GPIO64_PR3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO65_PR4, \"SOC_GPIO65_PR4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO66_PR5, \"SOC_GPIO66_PR5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO67_PR6, \"SOC_GPIO67_PR6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO68_PR7, \"SOC_GPIO68_PR7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SCL_PS0, \"GEN4_I2C_SCL_PS0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SDA_PS1, \"GEN4_I2C_SDA_PS1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO75_PS2, \"SOC_GPIO75_PS2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PS3, \"GEN7_I2C_SCL_PS3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PS4, \"GEN7_I2C_SDA_PS4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO78_PS5, \"SOC_GPIO78_PS5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PS6, \"GEN9_I2C_SCL_PS6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PS7, \"GEN9_I2C_SDA_PS7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO81_PT0, \"SOC_GPIO81_PT0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PT1, \"SOC_GPIO36_PT1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PT2, \"SOC_GPIO53_PT2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PT3, \"SOC_GPIO38_PT3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PT4, \"SOC_GPIO40_PT4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PT5, \"SOC_GPIO34_PT5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PT6, \"USB_VBUS_EN0_PT6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PT7, \"USB_VBUS_EN1_PT7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PU0, \"SDMMC1_CLK_PU0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PU1, \"SDMMC1_CMD_PU1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PU2, \"SDMMC1_DAT0_PU2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PU3, \"SDMMC1_DAT1_PU3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PU4, \"SDMMC1_DAT2_PU4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PU5, \"SDMMC1_DAT3_PU5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PV0, \"UFS0_REF_CLK_PV0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PV1, \"UFS0_RST_N_PV1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, \"PEX_L0_CLKREQ_N_PW0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PW1, \"PEX_L0_RST_N_PW1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, \"PEX_L1_CLKREQ_N_PW2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PW3, \"PEX_L1_RST_N_PW3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, \"PEX_L2_CLKREQ_N_PW4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PW5, \"PEX_L2_RST_N_PW5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, \"PEX_L3_CLKREQ_N_PW6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PW7, \"PEX_L3_RST_N_PW7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PX0, \"PEX_WAKE_N_PX0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PX1, \"DP_AUX_CH0_HPD_PX1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, \"SDMMC1_COMP\"),\n+};\n+\n+static const struct pinctrl_pin_desc tegra238_aon_pins[] = {\n+\tPINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA0, \"BOOTV_CTL_N_PAA0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA1, \"SOC_GPIO00_PAA1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA2, \"VCOMP_ALERT_PAA2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM1_PAA3, \"PWM1_PAA3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA4, \"BATT_OC_PAA4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PAA5, \"SOC_GPIO04_PAA5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PAA6, \"SOC_GPIO25_PAA6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PAA7, \"SOC_GPIO26_PAA7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PBB0, \"HDMI_CEC_PBB0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, \"SPI2_SCK_PCC0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, \"SPI2_MISO_PCC1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, \"SPI2_MOSI_PCC2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, \"SPI2_CS0_PCC3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PCC4, \"SPI2_CS1_PCC4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, \"UART3_TX_PCC5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, \"UART3_RX_PCC6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, \"GEN2_I2C_SCL_PCC7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, \"GEN2_I2C_SDA_PDD0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, \"GEN8_I2C_SCL_PDD1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, \"GEN8_I2C_SDA_PDD2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PDD3, \"TOUCH_CLK_PDD3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PDD4, \"DMIC1_CLK_PDD4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PDD5, \"DMIC1_DAT_PDD5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PDD6, \"SOC_GPIO19_PDD6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM2_PDD7, \"PWM2_PDD7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM3_PEE0, \"PWM3_PEE0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_PWM7_PEE1, \"PWM7_PEE1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PEE2, \"SOC_GPIO49_PEE2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO82_PEE3, \"SOC_GPIO82_PEE3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PEE4, \"SOC_GPIO50_PEE4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO83_PEE5, \"SOC_GPIO83_PEE5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO69_PFF0, \"SOC_GPIO69_PFF0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO70_PFF1, \"SOC_GPIO70_PFF1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO71_PFF2, \"SOC_GPIO71_PFF2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO72_PFF3, \"SOC_GPIO72_PFF3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO73_PFF4, \"SOC_GPIO73_PFF4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO74_PFF5, \"SOC_GPIO74_PFF5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO80_PFF6, \"SOC_GPIO80_PFF6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO76_PFF7, \"SOC_GPIO76_PFF7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO77_PGG0, \"SOC_GPIO77_PGG0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO84_PGG1, \"SOC_GPIO84_PGG1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART2_TX_PGG2, \"UART2_TX_PGG2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART2_RX_PGG3, \"UART2_RX_PGG3\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART2_RTS_PGG4, \"UART2_RTS_PGG4\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART2_CTS_PGG5, \"UART2_CTS_PGG5\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO85_PGG6, \"SOC_GPIO85_PGG6\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_TX_PGG7, \"UART5_TX_PGG7\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_RX_PHH0, \"UART5_RX_PHH0\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_RTS_PHH1, \"UART5_RTS_PHH1\"),\n+\tPINCTRL_PIN(TEGRA_PIN_UART5_CTS_PHH2, \"UART5_CTS_PHH2\"),\n+\tPINCTRL_PIN(TEGRA_PIN_SOC_GPIO86_PHH3, \"SOC_GPIO86_PHH3\"),\n+};\n+\n+static const unsigned int gpu_pwr_req_pa0_pins[] = {\n+\tTEGRA_PIN_GPU_PWR_REQ_PA0,\n+};\n+\n+static const unsigned int gp_pwm5_pa1_pins[] = {\n+\tTEGRA_PIN_GP_PWM5_PA1,\n+};\n+\n+static const unsigned int gp_pwm6_pa2_pins[] = {\n+\tTEGRA_PIN_GP_PWM6_PA2,\n+};\n+\n+static const unsigned int spi3_sck_pa3_pins[] = {\n+\tTEGRA_PIN_SPI3_SCK_PA3,\n+};\n+\n+static const unsigned int spi3_miso_pa4_pins[] = {\n+\tTEGRA_PIN_SPI3_MISO_PA4,\n+};\n+\n+static const unsigned int spi3_mosi_pa5_pins[] = {\n+\tTEGRA_PIN_SPI3_MOSI_PA5,\n+};\n+\n+static const unsigned int spi3_cs0_pa6_pins[] = {\n+\tTEGRA_PIN_SPI3_CS0_PA6,\n+};\n+\n+static const unsigned int spi3_cs1_pa7_pins[] = {\n+\tTEGRA_PIN_SPI3_CS1_PA7,\n+};\n+\n+static const unsigned int spi1_sck_pb0_pins[] = {\n+\tTEGRA_PIN_SPI1_SCK_PB0,\n+};\n+\n+static const unsigned int spi1_miso_pb1_pins[] = {\n+\tTEGRA_PIN_SPI1_MISO_PB1,\n+};\n+\n+static const unsigned int spi1_mosi_pb2_pins[] = {\n+\tTEGRA_PIN_SPI1_MOSI_PB2,\n+};\n+\n+static const unsigned int spi1_cs0_pb3_pins[] = {\n+\tTEGRA_PIN_SPI1_CS0_PB3,\n+};\n+\n+static const unsigned int spi1_cs1_pb4_pins[] = {\n+\tTEGRA_PIN_SPI1_CS1_PB4,\n+};\n+\n+static const unsigned int pwr_i2c_scl_pc0_pins[] = {\n+\tTEGRA_PIN_PWR_I2C_SCL_PC0,\n+};\n+\n+static const unsigned int pwr_i2c_sda_pc1_pins[] = {\n+\tTEGRA_PIN_PWR_I2C_SDA_PC1,\n+};\n+\n+static const unsigned int extperiph1_clk_pc2_pins[] = {\n+\tTEGRA_PIN_EXTPERIPH1_CLK_PC2,\n+};\n+\n+static const unsigned int extperiph2_clk_pc3_pins[] = {\n+\tTEGRA_PIN_EXTPERIPH2_CLK_PC3,\n+};\n+\n+static const unsigned int cam_i2c_scl_pc4_pins[] = {\n+\tTEGRA_PIN_CAM_I2C_SCL_PC4,\n+};\n+\n+static const unsigned int cam_i2c_sda_pc5_pins[] = {\n+\tTEGRA_PIN_CAM_I2C_SDA_PC5,\n+};\n+\n+static const unsigned int soc_gpio23_pc6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO23_PC6,\n+};\n+\n+static const unsigned int soc_gpio24_pc7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO24_PC7,\n+};\n+\n+static const unsigned int soc_gpio27_pd0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO27_PD0,\n+};\n+\n+static const unsigned int soc_gpio55_pd1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO55_PD1,\n+};\n+\n+static const unsigned int soc_gpio29_pd2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO29_PD2,\n+};\n+\n+static const unsigned int soc_gpio33_pd3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO33_PD3,\n+};\n+\n+static const unsigned int soc_gpio32_pd4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO32_PD4,\n+};\n+\n+static const unsigned int soc_gpio35_pd5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO35_PD5,\n+};\n+\n+static const unsigned int soc_gpio37_pd6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO37_PD6,\n+};\n+\n+static const unsigned int soc_gpio56_pd7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO56_PD7,\n+};\n+\n+static const unsigned int uart1_tx_pe0_pins[] = {\n+\tTEGRA_PIN_UART1_TX_PE0,\n+};\n+\n+static const unsigned int uart1_rx_pe1_pins[] = {\n+\tTEGRA_PIN_UART1_RX_PE1,\n+};\n+\n+static const unsigned int uart1_rts_pe2_pins[] = {\n+\tTEGRA_PIN_UART1_RTS_PE2,\n+};\n+\n+static const unsigned int uart1_cts_pe3_pins[] = {\n+\tTEGRA_PIN_UART1_CTS_PE3,\n+};\n+\n+static const unsigned int soc_gpio13_pf0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO13_PF0,\n+};\n+\n+static const unsigned int soc_gpio14_pf1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO14_PF1,\n+};\n+\n+static const unsigned int soc_gpio15_pf2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO15_PF2,\n+};\n+\n+static const unsigned int soc_gpio16_pf3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO16_PF3,\n+};\n+\n+static const unsigned int soc_gpio17_pf4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO17_PF4,\n+};\n+\n+static const unsigned int soc_gpio18_pf5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO18_PF5,\n+};\n+\n+static const unsigned int soc_gpio20_pf6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO20_PF6,\n+};\n+\n+static const unsigned int soc_gpio21_pf7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO21_PF7,\n+};\n+\n+static const unsigned int soc_gpio22_pg0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO22_PG0,\n+};\n+\n+static const unsigned int soc_gpio06_pg1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO06_PG1,\n+};\n+\n+static const unsigned int uart4_tx_pg2_pins[] = {\n+\tTEGRA_PIN_UART4_TX_PG2,\n+};\n+\n+static const unsigned int uart4_rx_pg3_pins[] = {\n+\tTEGRA_PIN_UART4_RX_PG3,\n+};\n+\n+static const unsigned int uart4_rts_pg4_pins[] = {\n+\tTEGRA_PIN_UART4_RTS_PG4,\n+};\n+\n+static const unsigned int uart4_cts_pg5_pins[] = {\n+\tTEGRA_PIN_UART4_CTS_PG5,\n+};\n+\n+static const unsigned int soc_gpio41_pg6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO41_PG6,\n+};\n+\n+static const unsigned int soc_gpio42_pg7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO42_PG7,\n+};\n+\n+static const unsigned int soc_gpio43_ph0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO43_PH0,\n+};\n+\n+static const unsigned int soc_gpio44_ph1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO44_PH1,\n+};\n+\n+static const unsigned int gen1_i2c_scl_ph2_pins[] = {\n+\tTEGRA_PIN_GEN1_I2C_SCL_PH2,\n+};\n+\n+static const unsigned int gen1_i2c_sda_ph3_pins[] = {\n+\tTEGRA_PIN_GEN1_I2C_SDA_PH3,\n+};\n+\n+static const unsigned int cpu_pwr_req_ph4_pins[] = {\n+\tTEGRA_PIN_CPU_PWR_REQ_PH4,\n+};\n+\n+static const unsigned int soc_gpio07_ph5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO07_PH5,\n+};\n+\n+static const unsigned int dap3_clk_pj0_pins[] = {\n+\tTEGRA_PIN_DAP3_CLK_PJ0,\n+};\n+\n+static const unsigned int dap3_dout_pj1_pins[] = {\n+\tTEGRA_PIN_DAP3_DOUT_PJ1,\n+};\n+\n+static const unsigned int dap3_din_pj2_pins[] = {\n+\tTEGRA_PIN_DAP3_DIN_PJ2,\n+};\n+\n+static const unsigned int dap3_fs_pj3_pins[] = {\n+\tTEGRA_PIN_DAP3_FS_PJ3,\n+};\n+\n+static const unsigned int soc_gpio57_pj4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO57_PJ4,\n+};\n+\n+static const unsigned int soc_gpio58_pj5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO58_PJ5,\n+};\n+\n+static const unsigned int soc_gpio59_pj6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO59_PJ6,\n+};\n+\n+static const unsigned int soc_gpio60_pj7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO60_PJ7,\n+};\n+\n+static const unsigned int soc_gpio45_pk0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO45_PK0,\n+};\n+\n+static const unsigned int soc_gpio46_pk1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO46_PK1,\n+};\n+\n+static const unsigned int soc_gpio47_pk2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO47_PK2,\n+};\n+\n+static const unsigned int soc_gpio48_pk3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO48_PK3,\n+};\n+\n+static const unsigned int qspi0_sck_pl0_pins[] = {\n+\tTEGRA_PIN_QSPI0_SCK_PL0,\n+};\n+\n+static const unsigned int qspi0_io0_pl1_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO0_PL1,\n+};\n+\n+static const unsigned int qspi0_io1_pl2_pins[] = {\n+\tTEGRA_PIN_QSPI0_IO1_PL2,\n+};\n+\n+static const unsigned int qspi0_cs_n_pl3_pins[] = {\n+\tTEGRA_PIN_QSPI0_CS_N_PL3,\n+};\n+\n+static const unsigned int soc_gpio152_pl4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO152_PL4,\n+};\n+\n+static const unsigned int soc_gpio153_pl5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO153_PL5,\n+};\n+\n+static const unsigned int soc_gpio154_pl6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO154_PL6,\n+};\n+\n+static const unsigned int soc_gpio155_pl7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO155_PL7,\n+};\n+\n+static const unsigned int soc_gpio156_pm0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO156_PM0,\n+};\n+\n+static const unsigned int soc_gpio157_pm1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO157_PM1,\n+};\n+\n+static const unsigned int soc_gpio158_pm2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO158_PM2,\n+};\n+\n+static const unsigned int soc_gpio159_pm3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO159_PM3,\n+};\n+\n+static const unsigned int soc_gpio160_pm4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO160_PM4,\n+};\n+\n+static const unsigned int soc_gpio161_pm5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO161_PM5,\n+};\n+\n+static const unsigned int soc_gpio162_pm6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO162_PM6,\n+};\n+\n+static const unsigned int uart7_tx_pm7_pins[] = {\n+\tTEGRA_PIN_UART7_TX_PM7,\n+};\n+\n+static const unsigned int uart7_rx_pn0_pins[] = {\n+\tTEGRA_PIN_UART7_RX_PN0,\n+};\n+\n+static const unsigned int uart7_rts_pn1_pins[] = {\n+\tTEGRA_PIN_UART7_RTS_PN1,\n+};\n+\n+static const unsigned int uart7_cts_pn2_pins[] = {\n+\tTEGRA_PIN_UART7_CTS_PN2,\n+};\n+\n+static const unsigned int soc_gpio167_pp0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO167_PP0,\n+};\n+\n+static const unsigned int soc_gpio168_pp1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO168_PP1,\n+};\n+\n+static const unsigned int soc_gpio169_pp2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO169_PP2,\n+};\n+\n+static const unsigned int soc_gpio170_pp3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO170_PP3,\n+};\n+\n+static const unsigned int dap4_sclk_pp4_pins[] = {\n+\tTEGRA_PIN_DAP4_SCLK_PP4,\n+};\n+\n+static const unsigned int dap4_dout_pp5_pins[] = {\n+\tTEGRA_PIN_DAP4_DOUT_PP5,\n+};\n+\n+static const unsigned int dap4_din_pp6_pins[] = {\n+\tTEGRA_PIN_DAP4_DIN_PP6,\n+};\n+\n+static const unsigned int dap4_fs_pp7_pins[] = {\n+\tTEGRA_PIN_DAP4_FS_PP7,\n+};\n+\n+static const unsigned int soc_gpio171_pq0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO171_PQ0,\n+};\n+\n+static const unsigned int soc_gpio172_pq1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO172_PQ1,\n+};\n+\n+static const unsigned int soc_gpio173_pq2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO173_PQ2,\n+};\n+\n+static const unsigned int soc_gpio61_pr0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO61_PR0,\n+};\n+\n+static const unsigned int soc_gpio62_pr1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO62_PR1,\n+};\n+\n+static const unsigned int soc_gpio63_pr2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO63_PR2,\n+};\n+\n+static const unsigned int soc_gpio64_pr3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO64_PR3,\n+};\n+\n+static const unsigned int soc_gpio65_pr4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO65_PR4,\n+};\n+\n+static const unsigned int soc_gpio66_pr5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO66_PR5,\n+};\n+\n+static const unsigned int soc_gpio67_pr6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO67_PR6,\n+};\n+\n+static const unsigned int soc_gpio68_pr7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO68_PR7,\n+};\n+\n+static const unsigned int gen4_i2c_scl_ps0_pins[] = {\n+\tTEGRA_PIN_GEN4_I2C_SCL_PS0,\n+};\n+\n+static const unsigned int gen4_i2c_sda_ps1_pins[] = {\n+\tTEGRA_PIN_GEN4_I2C_SDA_PS1,\n+};\n+\n+static const unsigned int soc_gpio75_ps2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO75_PS2,\n+};\n+\n+static const unsigned int gen7_i2c_scl_ps3_pins[] = {\n+\tTEGRA_PIN_GEN7_I2C_SCL_PS3,\n+};\n+\n+static const unsigned int gen7_i2c_sda_ps4_pins[] = {\n+\tTEGRA_PIN_GEN7_I2C_SDA_PS4,\n+};\n+\n+static const unsigned int soc_gpio78_ps5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO78_PS5,\n+};\n+\n+static const unsigned int gen9_i2c_scl_ps6_pins[] = {\n+\tTEGRA_PIN_GEN9_I2C_SCL_PS6,\n+};\n+\n+static const unsigned int gen9_i2c_sda_ps7_pins[] = {\n+\tTEGRA_PIN_GEN9_I2C_SDA_PS7,\n+};\n+\n+static const unsigned int soc_gpio81_pt0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO81_PT0,\n+};\n+\n+static const unsigned int soc_gpio36_pt1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO36_PT1,\n+};\n+\n+static const unsigned int soc_gpio53_pt2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO53_PT2,\n+};\n+\n+static const unsigned int soc_gpio38_pt3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO38_PT3,\n+};\n+\n+static const unsigned int soc_gpio40_pt4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO40_PT4,\n+};\n+\n+static const unsigned int soc_gpio34_pt5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO34_PT5,\n+};\n+\n+static const unsigned int usb_vbus_en0_pt6_pins[] = {\n+\tTEGRA_PIN_USB_VBUS_EN0_PT6,\n+};\n+\n+static const unsigned int usb_vbus_en1_pt7_pins[] = {\n+\tTEGRA_PIN_USB_VBUS_EN1_PT7,\n+};\n+\n+static const unsigned int sdmmc1_clk_pu0_pins[] = {\n+\tTEGRA_PIN_SDMMC1_CLK_PU0,\n+};\n+\n+static const unsigned int sdmmc1_cmd_pu1_pins[] = {\n+\tTEGRA_PIN_SDMMC1_CMD_PU1,\n+};\n+\n+static const unsigned int sdmmc1_dat0_pu2_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT0_PU2,\n+};\n+\n+static const unsigned int sdmmc1_dat1_pu3_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT1_PU3,\n+};\n+\n+static const unsigned int sdmmc1_dat2_pu4_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT2_PU4,\n+};\n+\n+static const unsigned int sdmmc1_dat3_pu5_pins[] = {\n+\tTEGRA_PIN_SDMMC1_DAT3_PU5,\n+};\n+\n+static const unsigned int ufs0_ref_clk_pv0_pins[] = {\n+\tTEGRA_PIN_UFS0_REF_CLK_PV0,\n+};\n+\n+static const unsigned int ufs0_rst_n_pv1_pins[] = {\n+\tTEGRA_PIN_UFS0_RST_N_PV1,\n+};\n+\n+static const unsigned int pex_l0_clkreq_n_pw0_pins[] = {\n+\tTEGRA_PIN_PEX_L0_CLKREQ_N_PW0,\n+};\n+\n+static const unsigned int pex_l0_rst_n_pw1_pins[] = {\n+\tTEGRA_PIN_PEX_L0_RST_N_PW1,\n+};\n+\n+static const unsigned int pex_l1_clkreq_n_pw2_pins[] = {\n+\tTEGRA_PIN_PEX_L1_CLKREQ_N_PW2,\n+};\n+\n+static const unsigned int pex_l1_rst_n_pw3_pins[] = {\n+\tTEGRA_PIN_PEX_L1_RST_N_PW3,\n+};\n+\n+static const unsigned int pex_l2_clkreq_n_pw4_pins[] = {\n+\tTEGRA_PIN_PEX_L2_CLKREQ_N_PW4,\n+};\n+\n+static const unsigned int pex_l2_rst_n_pw5_pins[] = {\n+\tTEGRA_PIN_PEX_L2_RST_N_PW5,\n+};\n+\n+static const unsigned int pex_l3_clkreq_n_pw6_pins[] = {\n+\tTEGRA_PIN_PEX_L3_CLKREQ_N_PW6,\n+};\n+\n+static const unsigned int pex_l3_rst_n_pw7_pins[] = {\n+\tTEGRA_PIN_PEX_L3_RST_N_PW7,\n+};\n+\n+static const unsigned int pex_wake_n_px0_pins[] = {\n+\tTEGRA_PIN_PEX_WAKE_N_PX0,\n+};\n+\n+static const unsigned int dp_aux_ch0_hpd_px1_pins[] = {\n+\tTEGRA_PIN_DP_AUX_CH0_HPD_PX1,\n+};\n+\n+static const unsigned int bootv_ctl_n_paa0_pins[] = {\n+\tTEGRA_PIN_BOOTV_CTL_N_PAA0,\n+};\n+\n+static const unsigned int soc_gpio00_paa1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO00_PAA1,\n+};\n+\n+static const unsigned int vcomp_alert_paa2_pins[] = {\n+\tTEGRA_PIN_VCOMP_ALERT_PAA2,\n+};\n+\n+static const unsigned int pwm1_paa3_pins[] = {\n+\tTEGRA_PIN_PWM1_PAA3,\n+};\n+\n+static const unsigned int batt_oc_paa4_pins[] = {\n+\tTEGRA_PIN_BATT_OC_PAA4,\n+};\n+\n+static const unsigned int soc_gpio04_paa5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO04_PAA5,\n+};\n+\n+static const unsigned int soc_gpio25_paa6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO25_PAA6,\n+};\n+\n+static const unsigned int soc_gpio26_paa7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO26_PAA7,\n+};\n+\n+static const unsigned int hdmi_cec_pbb0_pins[] = {\n+\tTEGRA_PIN_HDMI_CEC_PBB0,\n+};\n+\n+static const unsigned int spi2_sck_pcc0_pins[] = {\n+\tTEGRA_PIN_SPI2_SCK_PCC0,\n+};\n+\n+static const unsigned int spi2_miso_pcc1_pins[] = {\n+\tTEGRA_PIN_SPI2_MISO_PCC1,\n+};\n+\n+static const unsigned int spi2_mosi_pcc2_pins[] = {\n+\tTEGRA_PIN_SPI2_MOSI_PCC2,\n+};\n+\n+static const unsigned int spi2_cs0_pcc3_pins[] = {\n+\tTEGRA_PIN_SPI2_CS0_PCC3,\n+};\n+\n+static const unsigned int spi2_cs1_pcc4_pins[] = {\n+\tTEGRA_PIN_SPI2_CS1_PCC4,\n+};\n+\n+static const unsigned int uart3_tx_pcc5_pins[] = {\n+\tTEGRA_PIN_UART3_TX_PCC5,\n+};\n+\n+static const unsigned int uart3_rx_pcc6_pins[] = {\n+\tTEGRA_PIN_UART3_RX_PCC6,\n+};\n+\n+static const unsigned int gen2_i2c_scl_pcc7_pins[] = {\n+\tTEGRA_PIN_GEN2_I2C_SCL_PCC7,\n+};\n+\n+static const unsigned int gen2_i2c_sda_pdd0_pins[] = {\n+\tTEGRA_PIN_GEN2_I2C_SDA_PDD0,\n+};\n+\n+static const unsigned int gen8_i2c_scl_pdd1_pins[] = {\n+\tTEGRA_PIN_GEN8_I2C_SCL_PDD1,\n+};\n+\n+static const unsigned int gen8_i2c_sda_pdd2_pins[] = {\n+\tTEGRA_PIN_GEN8_I2C_SDA_PDD2,\n+};\n+\n+static const unsigned int touch_clk_pdd3_pins[] = {\n+\tTEGRA_PIN_TOUCH_CLK_PDD3,\n+};\n+\n+static const unsigned int dmic1_clk_pdd4_pins[] = {\n+\tTEGRA_PIN_DMIC1_CLK_PDD4,\n+};\n+\n+static const unsigned int dmic1_dat_pdd5_pins[] = {\n+\tTEGRA_PIN_DMIC1_DAT_PDD5,\n+};\n+\n+static const unsigned int soc_gpio19_pdd6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO19_PDD6,\n+};\n+\n+static const unsigned int pwm2_pdd7_pins[] = {\n+\tTEGRA_PIN_PWM2_PDD7,\n+};\n+\n+static const unsigned int pwm3_pee0_pins[] = {\n+\tTEGRA_PIN_PWM3_PEE0,\n+};\n+\n+static const unsigned int pwm7_pee1_pins[] = {\n+\tTEGRA_PIN_PWM7_PEE1,\n+};\n+\n+static const unsigned int soc_gpio49_pee2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO49_PEE2,\n+};\n+\n+static const unsigned int soc_gpio82_pee3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO82_PEE3,\n+};\n+\n+static const unsigned int soc_gpio50_pee4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO50_PEE4,\n+};\n+\n+static const unsigned int soc_gpio83_pee5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO83_PEE5,\n+};\n+\n+static const unsigned int soc_gpio69_pff0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO69_PFF0,\n+};\n+\n+static const unsigned int soc_gpio70_pff1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO70_PFF1,\n+};\n+\n+static const unsigned int soc_gpio71_pff2_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO71_PFF2,\n+};\n+\n+static const unsigned int soc_gpio72_pff3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO72_PFF3,\n+};\n+\n+static const unsigned int soc_gpio73_pff4_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO73_PFF4,\n+};\n+\n+static const unsigned int soc_gpio74_pff5_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO74_PFF5,\n+};\n+\n+static const unsigned int soc_gpio80_pff6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO80_PFF6,\n+};\n+\n+static const unsigned int soc_gpio76_pff7_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO76_PFF7,\n+};\n+\n+static const unsigned int soc_gpio77_pgg0_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO77_PGG0,\n+};\n+\n+static const unsigned int soc_gpio84_pgg1_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO84_PGG1,\n+};\n+\n+static const unsigned int uart2_tx_pgg2_pins[] = {\n+\tTEGRA_PIN_UART2_TX_PGG2,\n+};\n+\n+static const unsigned int uart2_rx_pgg3_pins[] = {\n+\tTEGRA_PIN_UART2_RX_PGG3,\n+};\n+\n+static const unsigned int uart2_rts_pgg4_pins[] = {\n+\tTEGRA_PIN_UART2_RTS_PGG4,\n+};\n+\n+static const unsigned int uart2_cts_pgg5_pins[] = {\n+\tTEGRA_PIN_UART2_CTS_PGG5,\n+};\n+\n+static const unsigned int soc_gpio85_pgg6_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO85_PGG6,\n+};\n+\n+static const unsigned int uart5_tx_pgg7_pins[] = {\n+\tTEGRA_PIN_UART5_TX_PGG7,\n+};\n+\n+static const unsigned int uart5_rx_phh0_pins[] = {\n+\tTEGRA_PIN_UART5_RX_PHH0,\n+};\n+\n+static const unsigned int uart5_rts_phh1_pins[] = {\n+\tTEGRA_PIN_UART5_RTS_PHH1,\n+};\n+\n+static const unsigned int uart5_cts_phh2_pins[] = {\n+\tTEGRA_PIN_UART5_CTS_PHH2,\n+};\n+\n+static const unsigned int soc_gpio86_phh3_pins[] = {\n+\tTEGRA_PIN_SOC_GPIO86_PHH3,\n+};\n+\n+static const unsigned int sdmmc1_comp_pins[] = {\n+\tTEGRA_PIN_SDMMC1_COMP,\n+};\n+\n+/* Define unique ID for each function */\n+enum tegra_mux_dt {\n+\tTEGRA_MUX_DCA_VSYNC,\n+\tTEGRA_MUX_DCA_HSYNC,\n+\tTEGRA_MUX_DISPLAYA,\n+\tTEGRA_MUX_RSVD0,\n+\tTEGRA_MUX_I2C7_CLK,\n+\tTEGRA_MUX_I2C7_DAT,\n+\tTEGRA_MUX_I2C4_DAT,\n+\tTEGRA_MUX_I2C4_CLK,\n+\tTEGRA_MUX_I2C9_DAT,\n+\tTEGRA_MUX_I2C9_CLK,\n+\tTEGRA_MUX_USB_VBUS_EN0,\n+\tTEGRA_MUX_USB_VBUS_EN1,\n+\tTEGRA_MUX_SPI3_DIN,\n+\tTEGRA_MUX_SPI1_CS0,\n+\tTEGRA_MUX_SPI3_CS0,\n+\tTEGRA_MUX_SPI1_DIN,\n+\tTEGRA_MUX_SPI3_CS1,\n+\tTEGRA_MUX_SPI1_SCK,\n+\tTEGRA_MUX_SPI3_SCK,\n+\tTEGRA_MUX_SPI1_CS1,\n+\tTEGRA_MUX_SPI1_DOUT,\n+\tTEGRA_MUX_SPI3_DOUT,\n+\tTEGRA_MUX_GP_PWM5,\n+\tTEGRA_MUX_GP_PWM6,\n+\tTEGRA_MUX_EXTPERIPH2_CLK,\n+\tTEGRA_MUX_EXTPERIPH1_CLK,\n+\tTEGRA_MUX_I2C3_DAT,\n+\tTEGRA_MUX_I2C3_CLK,\n+\tTEGRA_MUX_EXTPERIPH4_CLK,\n+\tTEGRA_MUX_EXTPERIPH3_CLK,\n+\tTEGRA_MUX_DMIC2_DAT,\n+\tTEGRA_MUX_DMIC2_CLK,\n+\tTEGRA_MUX_UARTA_CTS,\n+\tTEGRA_MUX_UARTA_RTS,\n+\tTEGRA_MUX_UARTA_RXD,\n+\tTEGRA_MUX_UARTA_TXD,\n+\tTEGRA_MUX_I2C5_CLK,\n+\tTEGRA_MUX_I2C5_DAT,\n+\tTEGRA_MUX_UARTD_CTS,\n+\tTEGRA_MUX_UARTD_RTS,\n+\tTEGRA_MUX_UARTD_RXD,\n+\tTEGRA_MUX_UARTD_TXD,\n+\tTEGRA_MUX_I2C1_CLK,\n+\tTEGRA_MUX_I2C1_DAT,\n+\tTEGRA_MUX_SDMMC1_CD,\n+\tTEGRA_MUX_I2S2_SCLK,\n+\tTEGRA_MUX_I2S2_SDATA_OUT,\n+\tTEGRA_MUX_I2S2_SDATA_IN,\n+\tTEGRA_MUX_I2S2_LRCK,\n+\tTEGRA_MUX_I2S4_SCLK,\n+\tTEGRA_MUX_I2S4_SDATA_OUT,\n+\tTEGRA_MUX_I2S4_SDATA_IN,\n+\tTEGRA_MUX_I2S4_LRCK,\n+\tTEGRA_MUX_I2S1_SCLK,\n+\tTEGRA_MUX_I2S1_SDATA_OUT,\n+\tTEGRA_MUX_I2S1_SDATA_IN,\n+\tTEGRA_MUX_I2S1_LRCK,\n+\tTEGRA_MUX_AUD_MCLK,\n+\tTEGRA_MUX_I2S3_LRCK,\n+\tTEGRA_MUX_I2S3_SCLK,\n+\tTEGRA_MUX_I2S3_SDATA_IN,\n+\tTEGRA_MUX_I2S3_SDATA_OUT,\n+\tTEGRA_MUX_PE2_CLKREQ_L,\n+\tTEGRA_MUX_PE1_CLKREQ_L,\n+\tTEGRA_MUX_PE1_RST_L,\n+\tTEGRA_MUX_PE0_CLKREQ_L,\n+\tTEGRA_MUX_PE0_RST_L,\n+\tTEGRA_MUX_PE2_RST_L,\n+\tTEGRA_MUX_PE3_CLKREQ_L,\n+\tTEGRA_MUX_PE3_RST_L,\n+\tTEGRA_MUX_DP_AUX_CH0_HPD,\n+\tTEGRA_MUX_QSPI0_IO0,\n+\tTEGRA_MUX_QSPI0_IO1,\n+\tTEGRA_MUX_QSPI0_SCK,\n+\tTEGRA_MUX_QSPI0_CS_N,\n+\tTEGRA_MUX_UARTG_CTS,\n+\tTEGRA_MUX_UARTG_RTS,\n+\tTEGRA_MUX_UARTG_TXD,\n+\tTEGRA_MUX_UARTG_RXD,\n+\tTEGRA_MUX_SDMMC1_CLK,\n+\tTEGRA_MUX_SDMMC1_CMD,\n+\tTEGRA_MUX_SDMMC1_COMP,\n+\tTEGRA_MUX_SDMMC1_DAT3,\n+\tTEGRA_MUX_SDMMC1_DAT2,\n+\tTEGRA_MUX_SDMMC1_DAT1,\n+\tTEGRA_MUX_SDMMC1_DAT0,\n+\tTEGRA_MUX_UFS0,\n+\tTEGRA_MUX_SOC_THERM_OC1,\n+\tTEGRA_MUX_HDMI_CEC,\n+\tTEGRA_MUX_GP_PWM4,\n+\tTEGRA_MUX_UARTC_RXD,\n+\tTEGRA_MUX_UARTC_TXD,\n+\tTEGRA_MUX_I2C8_DAT,\n+\tTEGRA_MUX_I2C8_CLK,\n+\tTEGRA_MUX_SPI2_DOUT,\n+\tTEGRA_MUX_I2C2_CLK,\n+\tTEGRA_MUX_SPI2_CS0,\n+\tTEGRA_MUX_I2C2_DAT,\n+\tTEGRA_MUX_SPI2_SCK,\n+\tTEGRA_MUX_SPI2_DIN,\n+\tTEGRA_MUX_PPC_MODE_1,\n+\tTEGRA_MUX_PPC_READY,\n+\tTEGRA_MUX_PPC_MODE_2,\n+\tTEGRA_MUX_PPC_CC,\n+\tTEGRA_MUX_PPC_MODE_0,\n+\tTEGRA_MUX_PPC_INT_N,\n+\tTEGRA_MUX_UARTE_TXD,\n+\tTEGRA_MUX_UARTE_RXD,\n+\tTEGRA_MUX_UARTB_TXD,\n+\tTEGRA_MUX_UARTB_RXD,\n+\tTEGRA_MUX_UARTB_CTS,\n+\tTEGRA_MUX_UARTB_RTS,\n+\tTEGRA_MUX_UARTE_CTS,\n+\tTEGRA_MUX_UARTE_RTS,\n+\tTEGRA_MUX_GP_PWM7,\n+\tTEGRA_MUX_GP_PWM2,\n+\tTEGRA_MUX_GP_PWM3,\n+\tTEGRA_MUX_GP_PWM1,\n+\tTEGRA_MUX_SPI2_CS1,\n+\tTEGRA_MUX_DMIC1_CLK,\n+\tTEGRA_MUX_DMIC1_DAT,\n+\tTEGRA_MUX_RSVD1,\n+\tTEGRA_MUX_DCB_HSYNC,\n+\tTEGRA_MUX_DCB_VSYNC,\n+\tTEGRA_MUX_SOC_THERM_OC4,\n+\tTEGRA_MUX_GP_PWM8,\n+\tTEGRA_MUX_NV_THERM_FAN_TACH0,\n+\tTEGRA_MUX_WDT_RESET_OUTA,\n+\tTEGRA_MUX_CCLA_LA_TRIGGER_MUX,\n+\tTEGRA_MUX_DSPK1_DAT,\n+\tTEGRA_MUX_DSPK1_CLK,\n+\tTEGRA_MUX_NV_THERM_FAN_TACH1,\n+\tTEGRA_MUX_DSPK0_DAT,\n+\tTEGRA_MUX_DSPK0_CLK,\n+\tTEGRA_MUX_I2S5_SCLK,\n+\tTEGRA_MUX_I2S6_LRCK,\n+\tTEGRA_MUX_I2S6_SDATA_IN,\n+\tTEGRA_MUX_I2S6_SCLK,\n+\tTEGRA_MUX_I2S6_SDATA_OUT,\n+\tTEGRA_MUX_I2S5_LRCK,\n+\tTEGRA_MUX_I2S5_SDATA_OUT,\n+\tTEGRA_MUX_I2S5_SDATA_IN,\n+\tTEGRA_MUX_SDMMC1_PE3_RST_L,\n+\tTEGRA_MUX_SDMMC1_PE3_CLKREQ_L,\n+\tTEGRA_MUX_TOUCH_CLK,\n+\tTEGRA_MUX_PPC_I2C_DAT,\n+\tTEGRA_MUX_WDT_RESET_OUTB,\n+\tTEGRA_MUX_SPI5_CS1,\n+\tTEGRA_MUX_PPC_RST_N,\n+\tTEGRA_MUX_PPC_I2C_CLK,\n+\tTEGRA_MUX_SPI4_CS1,\n+\tTEGRA_MUX_SOC_THERM_OC3,\n+\tTEGRA_MUX_SPI5_SCK,\n+\tTEGRA_MUX_SPI5_MISO,\n+\tTEGRA_MUX_SPI4_SCK,\n+\tTEGRA_MUX_SPI4_MISO,\n+\tTEGRA_MUX_SPI4_CS0,\n+\tTEGRA_MUX_SPI4_MOSI,\n+\tTEGRA_MUX_SPI5_CS0,\n+\tTEGRA_MUX_SPI5_MOSI,\n+\tTEGRA_MUX_LED_BLINK,\n+\tTEGRA_MUX_RSVD2,\n+\tTEGRA_MUX_DMIC3_CLK,\n+\tTEGRA_MUX_DMIC3_DAT,\n+\tTEGRA_MUX_DMIC4_CLK,\n+\tTEGRA_MUX_DMIC4_DAT,\n+\tTEGRA_MUX_TSC_EDGE_OUT0,\n+\tTEGRA_MUX_TSC_EDGE_OUT3,\n+\tTEGRA_MUX_TSC_EDGE_OUT1,\n+\tTEGRA_MUX_TSC_EDGE_OUT2,\n+\tTEGRA_MUX_DMIC5_CLK,\n+\tTEGRA_MUX_DMIC5_DAT,\n+\tTEGRA_MUX_RSVD3,\n+\tTEGRA_MUX_SDMMC1_WP,\n+\tTEGRA_MUX_TSC_EDGE_OUT0A,\n+\tTEGRA_MUX_TSC_EDGE_OUT0D,\n+\tTEGRA_MUX_TSC_EDGE_OUT0B,\n+\tTEGRA_MUX_TSC_EDGE_OUT0C,\n+\tTEGRA_MUX_SOC_THERM_OC2,\n+};\n+\n+/* Make list of each function name */\n+#define TEGRA_PIN_FUNCTION(lid) #lid\n+\n+static const char * const tegra238_functions[] = {\n+\tTEGRA_PIN_FUNCTION(dca_vsync),\n+\tTEGRA_PIN_FUNCTION(dca_hsync),\n+\tTEGRA_PIN_FUNCTION(displaya),\n+\tTEGRA_PIN_FUNCTION(rsvd0),\n+\tTEGRA_PIN_FUNCTION(i2c7_clk),\n+\tTEGRA_PIN_FUNCTION(i2c7_dat),\n+\tTEGRA_PIN_FUNCTION(i2c4_dat),\n+\tTEGRA_PIN_FUNCTION(i2c4_clk),\n+\tTEGRA_PIN_FUNCTION(i2c9_dat),\n+\tTEGRA_PIN_FUNCTION(i2c9_clk),\n+\tTEGRA_PIN_FUNCTION(usb_vbus_en0),\n+\tTEGRA_PIN_FUNCTION(usb_vbus_en1),\n+\tTEGRA_PIN_FUNCTION(spi3_din),\n+\tTEGRA_PIN_FUNCTION(spi1_cs0),\n+\tTEGRA_PIN_FUNCTION(spi3_cs0),\n+\tTEGRA_PIN_FUNCTION(spi1_din),\n+\tTEGRA_PIN_FUNCTION(spi3_cs1),\n+\tTEGRA_PIN_FUNCTION(spi1_sck),\n+\tTEGRA_PIN_FUNCTION(spi3_sck),\n+\tTEGRA_PIN_FUNCTION(spi1_cs1),\n+\tTEGRA_PIN_FUNCTION(spi1_dout),\n+\tTEGRA_PIN_FUNCTION(spi3_dout),\n+\tTEGRA_PIN_FUNCTION(gp_pwm5),\n+\tTEGRA_PIN_FUNCTION(gp_pwm6),\n+\tTEGRA_PIN_FUNCTION(extperiph2_clk),\n+\tTEGRA_PIN_FUNCTION(extperiph1_clk),\n+\tTEGRA_PIN_FUNCTION(i2c3_dat),\n+\tTEGRA_PIN_FUNCTION(i2c3_clk),\n+\tTEGRA_PIN_FUNCTION(extperiph4_clk),\n+\tTEGRA_PIN_FUNCTION(extperiph3_clk),\n+\tTEGRA_PIN_FUNCTION(dmic2_dat),\n+\tTEGRA_PIN_FUNCTION(dmic2_clk),\n+\tTEGRA_PIN_FUNCTION(uarta_cts),\n+\tTEGRA_PIN_FUNCTION(uarta_rts),\n+\tTEGRA_PIN_FUNCTION(uarta_rxd),\n+\tTEGRA_PIN_FUNCTION(uarta_txd),\n+\tTEGRA_PIN_FUNCTION(i2c5_clk),\n+\tTEGRA_PIN_FUNCTION(i2c5_dat),\n+\tTEGRA_PIN_FUNCTION(uartd_cts),\n+\tTEGRA_PIN_FUNCTION(uartd_rts),\n+\tTEGRA_PIN_FUNCTION(uartd_rxd),\n+\tTEGRA_PIN_FUNCTION(uartd_txd),\n+\tTEGRA_PIN_FUNCTION(i2c1_clk),\n+\tTEGRA_PIN_FUNCTION(i2c1_dat),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_cd),\n+\tTEGRA_PIN_FUNCTION(i2s2_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s2_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s2_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s2_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s4_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s4_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s4_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s4_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s1_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s1_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s1_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s1_lrck),\n+\tTEGRA_PIN_FUNCTION(aud_mclk),\n+\tTEGRA_PIN_FUNCTION(i2s3_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s3_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s3_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s3_sdata_out),\n+\tTEGRA_PIN_FUNCTION(pe2_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe1_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe1_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe0_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe0_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe2_rst_l),\n+\tTEGRA_PIN_FUNCTION(pe3_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(pe3_rst_l),\n+\tTEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),\n+\tTEGRA_PIN_FUNCTION(qspi0_io0),\n+\tTEGRA_PIN_FUNCTION(qspi0_io1),\n+\tTEGRA_PIN_FUNCTION(qspi0_sck),\n+\tTEGRA_PIN_FUNCTION(qspi0_cs_n),\n+\tTEGRA_PIN_FUNCTION(uartg_cts),\n+\tTEGRA_PIN_FUNCTION(uartg_rts),\n+\tTEGRA_PIN_FUNCTION(uartg_txd),\n+\tTEGRA_PIN_FUNCTION(uartg_rxd),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_clk),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_cmd),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_comp),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat3),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat2),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat1),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_dat0),\n+\tTEGRA_PIN_FUNCTION(ufs0),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc1),\n+\tTEGRA_PIN_FUNCTION(hdmi_cec),\n+\tTEGRA_PIN_FUNCTION(gp_pwm4),\n+\tTEGRA_PIN_FUNCTION(uartc_rxd),\n+\tTEGRA_PIN_FUNCTION(uartc_txd),\n+\tTEGRA_PIN_FUNCTION(i2c8_dat),\n+\tTEGRA_PIN_FUNCTION(i2c8_clk),\n+\tTEGRA_PIN_FUNCTION(spi2_dout),\n+\tTEGRA_PIN_FUNCTION(i2c2_clk),\n+\tTEGRA_PIN_FUNCTION(spi2_cs0),\n+\tTEGRA_PIN_FUNCTION(i2c2_dat),\n+\tTEGRA_PIN_FUNCTION(spi2_sck),\n+\tTEGRA_PIN_FUNCTION(spi2_din),\n+\tTEGRA_PIN_FUNCTION(ppc_mode_1),\n+\tTEGRA_PIN_FUNCTION(ppc_ready),\n+\tTEGRA_PIN_FUNCTION(ppc_mode_2),\n+\tTEGRA_PIN_FUNCTION(ppc_cc),\n+\tTEGRA_PIN_FUNCTION(ppc_mode_0),\n+\tTEGRA_PIN_FUNCTION(ppc_int_n),\n+\tTEGRA_PIN_FUNCTION(uarte_txd),\n+\tTEGRA_PIN_FUNCTION(uarte_rxd),\n+\tTEGRA_PIN_FUNCTION(uartb_txd),\n+\tTEGRA_PIN_FUNCTION(uartb_rxd),\n+\tTEGRA_PIN_FUNCTION(uartb_cts),\n+\tTEGRA_PIN_FUNCTION(uartb_rts),\n+\tTEGRA_PIN_FUNCTION(uarte_cts),\n+\tTEGRA_PIN_FUNCTION(uarte_rts),\n+\tTEGRA_PIN_FUNCTION(gp_pwm7),\n+\tTEGRA_PIN_FUNCTION(gp_pwm2),\n+\tTEGRA_PIN_FUNCTION(gp_pwm3),\n+\tTEGRA_PIN_FUNCTION(gp_pwm1),\n+\tTEGRA_PIN_FUNCTION(spi2_cs1),\n+\tTEGRA_PIN_FUNCTION(dmic1_clk),\n+\tTEGRA_PIN_FUNCTION(dmic1_dat),\n+\tTEGRA_PIN_FUNCTION(rsvd1),\n+\tTEGRA_PIN_FUNCTION(dcb_hsync),\n+\tTEGRA_PIN_FUNCTION(dcb_vsync),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc4),\n+\tTEGRA_PIN_FUNCTION(gp_pwm8),\n+\tTEGRA_PIN_FUNCTION(nv_therm_fan_tach0),\n+\tTEGRA_PIN_FUNCTION(wdt_reset_outa),\n+\tTEGRA_PIN_FUNCTION(ccla_la_trigger_mux),\n+\tTEGRA_PIN_FUNCTION(dspk1_dat),\n+\tTEGRA_PIN_FUNCTION(dspk1_clk),\n+\tTEGRA_PIN_FUNCTION(nv_therm_fan_tach1),\n+\tTEGRA_PIN_FUNCTION(dspk0_dat),\n+\tTEGRA_PIN_FUNCTION(dspk0_clk),\n+\tTEGRA_PIN_FUNCTION(i2s5_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s6_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s6_sdata_in),\n+\tTEGRA_PIN_FUNCTION(i2s6_sclk),\n+\tTEGRA_PIN_FUNCTION(i2s6_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s5_lrck),\n+\tTEGRA_PIN_FUNCTION(i2s5_sdata_out),\n+\tTEGRA_PIN_FUNCTION(i2s5_sdata_in),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_pe3_rst_l),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_pe3_clkreq_l),\n+\tTEGRA_PIN_FUNCTION(touch_clk),\n+\tTEGRA_PIN_FUNCTION(ppc_i2c_dat),\n+\tTEGRA_PIN_FUNCTION(wdt_reset_outb),\n+\tTEGRA_PIN_FUNCTION(spi5_cs1),\n+\tTEGRA_PIN_FUNCTION(ppc_rst_n),\n+\tTEGRA_PIN_FUNCTION(ppc_i2c_clk),\n+\tTEGRA_PIN_FUNCTION(spi4_cs1),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc3),\n+\tTEGRA_PIN_FUNCTION(spi5_sck),\n+\tTEGRA_PIN_FUNCTION(spi5_miso),\n+\tTEGRA_PIN_FUNCTION(spi4_sck),\n+\tTEGRA_PIN_FUNCTION(spi4_miso),\n+\tTEGRA_PIN_FUNCTION(spi4_cs0),\n+\tTEGRA_PIN_FUNCTION(spi4_mosi),\n+\tTEGRA_PIN_FUNCTION(spi5_cs0),\n+\tTEGRA_PIN_FUNCTION(spi5_mosi),\n+\tTEGRA_PIN_FUNCTION(led_blink),\n+\tTEGRA_PIN_FUNCTION(rsvd2),\n+\tTEGRA_PIN_FUNCTION(dmic3_clk),\n+\tTEGRA_PIN_FUNCTION(dmic3_dat),\n+\tTEGRA_PIN_FUNCTION(dmic4_clk),\n+\tTEGRA_PIN_FUNCTION(dmic4_dat),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out3),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out1),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out2),\n+\tTEGRA_PIN_FUNCTION(dmic5_clk),\n+\tTEGRA_PIN_FUNCTION(dmic5_dat),\n+\tTEGRA_PIN_FUNCTION(rsvd3),\n+\tTEGRA_PIN_FUNCTION(sdmmc1_wp),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0a),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0d),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0b),\n+\tTEGRA_PIN_FUNCTION(tsc_edge_out0c),\n+\tTEGRA_PIN_FUNCTION(soc_therm_oc2),\n+};\n+\n+#define PINGROUP_REG_Y(r) ((r))\n+#define PINGROUP_REG_N(r) -1\n+\n+#define DRV_PINGROUP_Y(r) ((r))\n+\n+#define DRV_PINGROUP_ENTRY_N\t\t\t\t\t\\\n+\t\t.drv_reg = -1,\t\t\t\t\t\\\n+\t\t.drv_bank = -1,\t\t\t\t\t\\\n+\t\t.drvdn_bit = -1,\t\t\t\t\\\n+\t\t.drvup_bit = -1,\t\t\t\t\\\n+\t\t.slwr_bit = -1,\t\t\t\t\t\\\n+\t\t.slwf_bit = -1\n+\n+#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b,\t\\\n+\t\t\t     drvup_w, slwr_b, slwr_w, slwf_b,\t\\\n+\t\t\t     slwf_w, bank)\t\t\t\\\n+\t\t.drv_reg = DRV_PINGROUP_Y(r),\t\t\t\\\n+\t\t.drv_bank = bank,\t\t\t\t\\\n+\t\t.drvdn_bit = drvdn_b,\t\t\t\t\\\n+\t\t.drvdn_width = drvdn_w,\t\t\t\t\\\n+\t\t.drvup_bit = drvup_b,\t\t\t\t\\\n+\t\t.drvup_width = drvup_w,\t\t\t\t\\\n+\t\t.slwr_bit = slwr_b,\t\t\t\t\\\n+\t\t.slwr_width = slwr_w,\t\t\t\t\\\n+\t\t.slwf_bit = slwf_b,\t\t\t\t\\\n+\t\t.slwf_width = slwf_w\n+\n+#define PIN_PINGROUP_ENTRY_N\t\t\t\t\t\\\n+\t\t.mux_reg = -1,\t\t\t\t\t\\\n+\t\t.pupd_reg = -1,\t\t\t\t\t\\\n+\t\t.tri_reg = -1,\t\t\t\t\t\\\n+\t\t.einput_bit = -1,\t\t\t\t\\\n+\t\t.e_io_hv_bit = -1,\t\t\t\t\\\n+\t\t.odrain_bit = -1,\t\t\t\t\\\n+\t\t.lock_bit = -1,\t\t\t\t\t\\\n+\t\t.parked_bit = -1,\t\t\t\t\\\n+\t\t.lpmd_bit = -1,\t\t\t\t\t\\\n+\t\t.drvtype_bit = -1,\t\t\t\t\\\n+\t\t.lpdr_bit = -1,\t\t\t\t\t\\\n+\t\t.pbias_buf_bit = -1,\t\t\t\t\\\n+\t\t.preemp_bit = -1,\t\t\t\t\\\n+\t\t.rfu_in_bit = -1\n+\n+#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input,\t\\\n+\t\t\t\te_lpdr, e_pbias_buf, gpio_sfio_sel,\t\\\n+\t\t\t\tschmitt_b)\t\t\t\t\\\n+\t\t.mux_reg = PINGROUP_REG_Y(r),\t\t\t\\\n+\t\t.lpmd_bit = -1,\t\t\t\t\t\\\n+\t\t.lock_bit = -1,\t\t\t\t\t\\\n+\t\t.hsm_bit = -1,\t\t\t\t\t\\\n+\t\t.mux_bank = bank,\t\t\t\t\\\n+\t\t.mux_bit = 0,\t\t\t\t\t\\\n+\t\t.pupd_reg = PINGROUP_REG_##pupd(r),\t\t\\\n+\t\t.pupd_bank = bank,\t\t\t\t\\\n+\t\t.pupd_bit = 2,\t\t\t\t\t\\\n+\t\t.tri_reg = PINGROUP_REG_Y(r),\t\t\t\\\n+\t\t.tri_bank = bank,\t\t\t\t\\\n+\t\t.tri_bit = 4,\t\t\t\t\t\\\n+\t\t.einput_bit = e_input,\t\t\t\t\\\n+\t\t.sfsel_bit = gpio_sfio_sel,\t\t\t\\\n+\t\t.schmitt_bit = schmitt_b,\t\t\t\\\n+\t\t.drvtype_bit = 13,\t\t\t\t\\\n+\t\t.lpdr_bit = e_lpdr,\n+\n+#define drive_soc_gpio36_pt1\t\tDRV_PINGROUP_ENTRY_Y(0x10004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio53_pt2\t\tDRV_PINGROUP_ENTRY_Y(0x1000c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio38_pt3\t\tDRV_PINGROUP_ENTRY_Y(0x1001c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio40_pt4\t\tDRV_PINGROUP_ENTRY_Y(0x1002c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio75_ps2\t\tDRV_PINGROUP_ENTRY_Y(0x10034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio81_pt0\t\tDRV_PINGROUP_ENTRY_Y(0x1003c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio78_ps5\t\tDRV_PINGROUP_ENTRY_Y(0x10044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio34_pt5\t\tDRV_PINGROUP_ENTRY_Y(0x1004c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen7_i2c_scl_ps3\t\tDRV_PINGROUP_ENTRY_Y(0x100a4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen7_i2c_sda_ps4\t\tDRV_PINGROUP_ENTRY_Y(0x100ac,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen4_i2c_sda_ps1\t\tDRV_PINGROUP_ENTRY_Y(0x100b4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen4_i2c_scl_ps0\t\tDRV_PINGROUP_ENTRY_Y(0x100bc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen9_i2c_sda_ps7\t\tDRV_PINGROUP_ENTRY_Y(0x100c4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen9_i2c_scl_ps6\t\tDRV_PINGROUP_ENTRY_Y(0x100cc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_usb_vbus_en0_pt6\t\tDRV_PINGROUP_ENTRY_Y(0x100d4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_usb_vbus_en1_pt7\t\tDRV_PINGROUP_ENTRY_Y(0x100dc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio61_pr0\t\tDRV_PINGROUP_ENTRY_Y(0x1f004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio62_pr1\t\tDRV_PINGROUP_ENTRY_Y(0x1f00c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio63_pr2\t\tDRV_PINGROUP_ENTRY_Y(0x1f014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio64_pr3\t\tDRV_PINGROUP_ENTRY_Y(0x1f01c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio65_pr4\t\tDRV_PINGROUP_ENTRY_Y(0x1f024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio66_pr5\t\tDRV_PINGROUP_ENTRY_Y(0x1f02c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio67_pr6\t\tDRV_PINGROUP_ENTRY_Y(0x1f034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio68_pr7\t\tDRV_PINGROUP_ENTRY_Y(0x1f03c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi3_miso_pa4\t\t    DRV_PINGROUP_ENTRY_Y(0xd004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi1_cs0_pb3\t\t    DRV_PINGROUP_ENTRY_Y(0xd00c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi3_cs0_pa6\t\t    DRV_PINGROUP_ENTRY_Y(0xd014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi1_miso_pb1\t\t    DRV_PINGROUP_ENTRY_Y(0xd01c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi3_cs1_pa7\t\t    DRV_PINGROUP_ENTRY_Y(0xd024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi1_sck_pb0\t\t    DRV_PINGROUP_ENTRY_Y(0xd02c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi3_sck_pa3\t\t    DRV_PINGROUP_ENTRY_Y(0xd034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi1_cs1_pb4\t\t    DRV_PINGROUP_ENTRY_Y(0xd03c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi1_mosi_pb2\t        DRV_PINGROUP_ENTRY_Y(0xd044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_spi3_mosi_pa5\t\t    DRV_PINGROUP_ENTRY_Y(0xd04c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gpu_pwr_req_pa0\t\tDRV_PINGROUP_ENTRY_Y(0xd054,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gp_pwm5_pa1\t\t    DRV_PINGROUP_ENTRY_Y(0xd05c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gp_pwm6_pa2\t\t    DRV_PINGROUP_ENTRY_Y(0xd064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_extperiph2_clk_pc3\tDRV_PINGROUP_ENTRY_Y(0x4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_extperiph1_clk_pc2\tDRV_PINGROUP_ENTRY_Y(0xc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_cam_i2c_sda_pc5\t\tDRV_PINGROUP_ENTRY_Y(0x14,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_cam_i2c_scl_pc4\t\tDRV_PINGROUP_ENTRY_Y(0x1c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio23_pc6\t\tDRV_PINGROUP_ENTRY_Y(0x24,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio24_pc7\t\tDRV_PINGROUP_ENTRY_Y(0x2c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio27_pd0\t\tDRV_PINGROUP_ENTRY_Y(0x44,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio29_pd2\t\tDRV_PINGROUP_ENTRY_Y(0x54,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio32_pd4\t\tDRV_PINGROUP_ENTRY_Y(0x6c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio33_pd3\t\tDRV_PINGROUP_ENTRY_Y(0x74,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio35_pd5\t\tDRV_PINGROUP_ENTRY_Y(0x7c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio37_pd6\t\tDRV_PINGROUP_ENTRY_Y(0x84,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio56_pd7\t\tDRV_PINGROUP_ENTRY_Y(0x8c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio55_pd1\t\tDRV_PINGROUP_ENTRY_Y(0x94,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart1_cts_pe3\t\t    DRV_PINGROUP_ENTRY_Y(0x9c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart1_rts_pe2\t\t    DRV_PINGROUP_ENTRY_Y(0xa4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart1_rx_pe1\t\t    DRV_PINGROUP_ENTRY_Y(0xac,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart1_tx_pe0\t\t    DRV_PINGROUP_ENTRY_Y(0xb4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pwr_i2c_scl_pc0\t\tDRV_PINGROUP_ENTRY_Y(0xbc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pwr_i2c_sda_pc1\t\tDRV_PINGROUP_ENTRY_Y(0xc4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_cpu_pwr_req_ph4\t\tDRV_PINGROUP_ENTRY_Y(0x4004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart4_cts_pg5\t\t    DRV_PINGROUP_ENTRY_Y(0x400c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart4_rts_pg4\t\t    DRV_PINGROUP_ENTRY_Y(0x4014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart4_rx_pg3\t\t    DRV_PINGROUP_ENTRY_Y(0x401c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart4_tx_pg2\t\t    DRV_PINGROUP_ENTRY_Y(0x4024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen1_i2c_scl_ph2\t\tDRV_PINGROUP_ENTRY_Y(0x402c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_gen1_i2c_sda_ph3\t\tDRV_PINGROUP_ENTRY_Y(0x4034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio20_pf6\t\tDRV_PINGROUP_ENTRY_Y(0x403c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio21_pf7\t\tDRV_PINGROUP_ENTRY_Y(0x4044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio22_pg0\t\tDRV_PINGROUP_ENTRY_Y(0x404c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio13_pf0\t\tDRV_PINGROUP_ENTRY_Y(0x4054,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio14_pf1\t\tDRV_PINGROUP_ENTRY_Y(0x405c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio15_pf2\t\tDRV_PINGROUP_ENTRY_Y(0x4064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio16_pf3\t\tDRV_PINGROUP_ENTRY_Y(0x406c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio17_pf4\t\tDRV_PINGROUP_ENTRY_Y(0x4074,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio18_pf5\t\tDRV_PINGROUP_ENTRY_Y(0x407c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio41_pg6\t\tDRV_PINGROUP_ENTRY_Y(0x408c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio42_pg7\t\tDRV_PINGROUP_ENTRY_Y(0x4094,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio43_ph0\t\tDRV_PINGROUP_ENTRY_Y(0x409c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio44_ph1\t\tDRV_PINGROUP_ENTRY_Y(0x40a4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio06_pg1\t\tDRV_PINGROUP_ENTRY_Y(0x40ac,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio07_ph5\t\tDRV_PINGROUP_ENTRY_Y(0x40b4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap4_sclk_pp4\t\t    DRV_PINGROUP_ENTRY_Y(0x2004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap4_dout_pp5\t\t    DRV_PINGROUP_ENTRY_Y(0x200c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap4_din_pp6\t\t    DRV_PINGROUP_ENTRY_Y(0x2014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap4_fs_pp7\t\t    DRV_PINGROUP_ENTRY_Y(0x201c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio167_pp0\t\tDRV_PINGROUP_ENTRY_Y(0x2044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio168_pp1\t\tDRV_PINGROUP_ENTRY_Y(0x204c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio169_pp2\t\tDRV_PINGROUP_ENTRY_Y(0x2054,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio170_pp3\t\tDRV_PINGROUP_ENTRY_Y(0x205c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio171_pq0\t\tDRV_PINGROUP_ENTRY_Y(0x2064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio172_pq1\t\tDRV_PINGROUP_ENTRY_Y(0x206c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio173_pq2\t\tDRV_PINGROUP_ENTRY_Y(0x2074,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio45_pk0\t\tDRV_PINGROUP_ENTRY_Y(0x18004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio46_pk1\t\tDRV_PINGROUP_ENTRY_Y(0x1800c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio47_pk2\t\tDRV_PINGROUP_ENTRY_Y(0x18014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio48_pk3\t\tDRV_PINGROUP_ENTRY_Y(0x1801c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio57_pj4\t\tDRV_PINGROUP_ENTRY_Y(0x18024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio58_pj5\t\tDRV_PINGROUP_ENTRY_Y(0x1802c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio59_pj6\t\tDRV_PINGROUP_ENTRY_Y(0x18034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio60_pj7\t\tDRV_PINGROUP_ENTRY_Y(0x1803c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap3_fs_pj3\t\t    DRV_PINGROUP_ENTRY_Y(0x18064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap3_clk_pj0\t\t    DRV_PINGROUP_ENTRY_Y(0x1806c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap3_din_pj2\t\t    DRV_PINGROUP_ENTRY_Y(0x18074,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dap3_dout_pj1\t\t    DRV_PINGROUP_ENTRY_Y(0x1807c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l2_clkreq_n_pw4\tDRV_PINGROUP_ENTRY_Y(0x7004,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_wake_n_px0\t\tDRV_PINGROUP_ENTRY_Y(0x700c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l1_clkreq_n_pw2\tDRV_PINGROUP_ENTRY_Y(0x7014,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l1_rst_n_pw3\t\tDRV_PINGROUP_ENTRY_Y(0x701c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l0_clkreq_n_pw0\tDRV_PINGROUP_ENTRY_Y(0x7024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l0_rst_n_pw1\t\tDRV_PINGROUP_ENTRY_Y(0x702c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l2_rst_n_pw5\t\tDRV_PINGROUP_ENTRY_Y(0x7034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l3_clkreq_n_pw6\tDRV_PINGROUP_ENTRY_Y(0x703c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_pex_l3_rst_n_pw7\t\tDRV_PINGROUP_ENTRY_Y(0x7044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_dp_aux_ch0_hpd_px1\tDRV_PINGROUP_ENTRY_Y(0x704c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_qspi0_io0_pl1\t\t    DRV_PINGROUP_ENTRY_Y(0xb004,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_qspi0_io1_pl2\t\t    DRV_PINGROUP_ENTRY_Y(0xb00c,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_qspi0_sck_pl0\t\t    DRV_PINGROUP_ENTRY_Y(0xb014,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_qspi0_cs_n_pl3\t\tDRV_PINGROUP_ENTRY_Y(0xb01c,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio156_pm0\t\tDRV_PINGROUP_ENTRY_Y(0xb024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio155_pl7\t\tDRV_PINGROUP_ENTRY_Y(0xb02c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio160_pm4\t\tDRV_PINGROUP_ENTRY_Y(0xb034,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio154_pl6\t\tDRV_PINGROUP_ENTRY_Y(0xb03c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio152_pl4\t\tDRV_PINGROUP_ENTRY_Y(0xb044,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio153_pl5\t\tDRV_PINGROUP_ENTRY_Y(0xb04c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio161_pm5\t\tDRV_PINGROUP_ENTRY_Y(0xb054,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio162_pm6\t\tDRV_PINGROUP_ENTRY_Y(0xb05c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio159_pm3\t\tDRV_PINGROUP_ENTRY_Y(0xb064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio157_pm1\t\tDRV_PINGROUP_ENTRY_Y(0xb06c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_soc_gpio158_pm2\t\tDRV_PINGROUP_ENTRY_Y(0xb074,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart7_cts_pn2\t\t    DRV_PINGROUP_ENTRY_Y(0xb07c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart7_rts_pn1\t\t    DRV_PINGROUP_ENTRY_Y(0xb084,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart7_tx_pm7\t\t    DRV_PINGROUP_ENTRY_Y(0xb08c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_uart7_rx_pn0\t\t    DRV_PINGROUP_ENTRY_Y(0xb094,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_clk_pu0\t\tDRV_PINGROUP_ENTRY_Y(0x8004,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_cmd_pu1\t\tDRV_PINGROUP_ENTRY_Y(0x800c,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_dat3_pu5\t\tDRV_PINGROUP_ENTRY_Y(0x801c,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_dat2_pu4\t\tDRV_PINGROUP_ENTRY_Y(0x8024,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_dat1_pu3\t\tDRV_PINGROUP_ENTRY_Y(0x802c,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_sdmmc1_dat0_pu2\t\tDRV_PINGROUP_ENTRY_Y(0x8034,\t28,\t2,\t30,\t2,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_ufs0_rst_n_pv1\t\tDRV_PINGROUP_ENTRY_Y(0x11004,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_ufs0_ref_clk_pv0\t\tDRV_PINGROUP_ENTRY_Y(0x1100c,\t12,\t5,\t24,\t5,\t-1,\t-1,\t-1,\t-1,\t0)\n+#define drive_batt_oc_paa4\t\t    DRV_PINGROUP_ENTRY_Y(0x1024,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_bootv_ctl_n_paa0\t\tDRV_PINGROUP_ENTRY_Y(0x102c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_vcomp_alert_paa2\t\tDRV_PINGROUP_ENTRY_Y(0x105c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_hdmi_cec_pbb0\t\t    DRV_PINGROUP_ENTRY_Y(0x1064,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_touch_clk_pdd3\t\tDRV_PINGROUP_ENTRY_Y(0x106c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart3_rx_pcc6\t\t    DRV_PINGROUP_ENTRY_Y(0x1074,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart3_tx_pcc5\t\t    DRV_PINGROUP_ENTRY_Y(0x107c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_gen8_i2c_sda_pdd2\t\tDRV_PINGROUP_ENTRY_Y(0x1084,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_gen8_i2c_scl_pdd1\t\tDRV_PINGROUP_ENTRY_Y(0x108c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_spi2_mosi_pcc2\t\tDRV_PINGROUP_ENTRY_Y(0x1094,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_gen2_i2c_scl_pcc7\t\tDRV_PINGROUP_ENTRY_Y(0x109c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_spi2_cs0_pcc3\t\t    DRV_PINGROUP_ENTRY_Y(0x10a4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_gen2_i2c_sda_pdd0\t\tDRV_PINGROUP_ENTRY_Y(0x10ac,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_spi2_sck_pcc0\t\t    DRV_PINGROUP_ENTRY_Y(0x10b4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_spi2_miso_pcc1\t\tDRV_PINGROUP_ENTRY_Y(0x10bc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio49_pee2\t\tDRV_PINGROUP_ENTRY_Y(0x10c4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio50_pee4\t\tDRV_PINGROUP_ENTRY_Y(0x10cc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio82_pee3\t\tDRV_PINGROUP_ENTRY_Y(0x10d4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio71_pff2\t\tDRV_PINGROUP_ENTRY_Y(0x10dc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio76_pff7\t\tDRV_PINGROUP_ENTRY_Y(0x10e4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio74_pff5\t\tDRV_PINGROUP_ENTRY_Y(0x10ec,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio00_paa1\t\tDRV_PINGROUP_ENTRY_Y(0x10f4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio19_pdd6\t\tDRV_PINGROUP_ENTRY_Y(0x10fc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio86_phh3\t\tDRV_PINGROUP_ENTRY_Y(0x1104,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio72_pff3\t\tDRV_PINGROUP_ENTRY_Y(0x110c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio77_pgg0\t\tDRV_PINGROUP_ENTRY_Y(0x1114,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio80_pff6\t\tDRV_PINGROUP_ENTRY_Y(0x111c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio84_pgg1\t\tDRV_PINGROUP_ENTRY_Y(0x1124,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio83_pee5\t\tDRV_PINGROUP_ENTRY_Y(0x112c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio73_pff4\t\tDRV_PINGROUP_ENTRY_Y(0x1134,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio70_pff1\t\tDRV_PINGROUP_ENTRY_Y(0x113c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio04_paa5\t\tDRV_PINGROUP_ENTRY_Y(0x1144,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio85_pgg6\t\tDRV_PINGROUP_ENTRY_Y(0x114c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio69_pff0\t\tDRV_PINGROUP_ENTRY_Y(0x1154,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio25_paa6\t\tDRV_PINGROUP_ENTRY_Y(0x115c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_soc_gpio26_paa7\t\tDRV_PINGROUP_ENTRY_Y(0x1164,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart5_tx_pgg7\t\t    DRV_PINGROUP_ENTRY_Y(0x116c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart5_rx_phh0\t\t    DRV_PINGROUP_ENTRY_Y(0x1174,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart2_tx_pgg2\t\t    DRV_PINGROUP_ENTRY_Y(0x117c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart2_rx_pgg3\t\t    DRV_PINGROUP_ENTRY_Y(0x1184,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart2_cts_pgg5\t\tDRV_PINGROUP_ENTRY_Y(0x118c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart2_rts_pgg4\t\tDRV_PINGROUP_ENTRY_Y(0x1194,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart5_cts_phh2\t\tDRV_PINGROUP_ENTRY_Y(0x119c,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_uart5_rts_phh1\t\tDRV_PINGROUP_ENTRY_Y(0x11a4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_pwm7_pee1\t\t\t    DRV_PINGROUP_ENTRY_Y(0x11ac,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_pwm2_pdd7\t\t\t    DRV_PINGROUP_ENTRY_Y(0x11b4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_pwm3_pee0\t\t\t    DRV_PINGROUP_ENTRY_Y(0x11bc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_pwm1_paa3\t\t\t    DRV_PINGROUP_ENTRY_Y(0x11c4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_spi2_cs1_pcc4\t\t    DRV_PINGROUP_ENTRY_Y(0x11cc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_dmic1_clk_pdd4\t\tDRV_PINGROUP_ENTRY_Y(0x11d4,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+#define drive_dmic1_dat_pdd5\t\tDRV_PINGROUP_ENTRY_Y(0x11dc,\t12,\t5,\t20,\t5,\t-1,\t-1,\t-1,\t-1,\t1)\n+\n+#define drive_sdmmc1_comp\t\tDRV_PINGROUP_ENTRY_N\n+\n+#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf,\t\\\n+\t\t\tgpio_sfio_sel, schmitt_b)\t\t\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.name = #pg_name,\t\t\t\t\t\\\n+\t\t.pins = pg_name##_pins,\t\t\t\t\t\\\n+\t\t.npins = ARRAY_SIZE(pg_name##_pins),\t\t\t\\\n+\t\t\t.funcs = {\t\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f0,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f1,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f2,\t\t\t\t\\\n+\t\t\t\tTEGRA_MUX_##f3,\t\t\t\t\\\n+\t\t\t},\t\t\t\t\t\t\\\n+\t\tPIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk,\t\\\n+\t\t\t\t\te_input, e_lpdr, e_pbias_buf,\t\\\n+\t\t\t\t\tgpio_sfio_sel, schmitt_b)\t\\\n+\t\tdrive_##pg_name,\t\t\t\t\t\\\n+\t}\n+\n+static const struct tegra_pingroup tegra238_groups[] = {\n+\tPINGROUP(soc_gpio36_pt1,\tDCA_VSYNC,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10000,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio53_pt2,\tDCA_HSYNC,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10008,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio38_pt3,\tDISPLAYA,\tDCB_HSYNC,\t\tRSVD2,\t\tRSVD3,\t\t0x10018,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio40_pt4,\tRSVD0,\t\tDCB_VSYNC,\t\tRSVD2,\t\tRSVD3,\t\t0x10028,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio75_ps2,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10030,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio81_pt0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10038,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio78_ps5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10040,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio34_pt5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10048,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen7_i2c_scl_ps3,\tI2C7_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100a0,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen7_i2c_sda_ps4,\tI2C7_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100a8,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen4_i2c_sda_ps1,\tI2C4_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100b0,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen4_i2c_scl_ps0,\tI2C4_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100b8,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen9_i2c_sda_ps7,\tI2C9_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100c0,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen9_i2c_scl_ps6,\tI2C9_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100c8,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(usb_vbus_en0_pt6,\tUSB_VBUS_EN0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100d0,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(usb_vbus_en1_pt7,\tUSB_VBUS_EN1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x100d8,\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio61_pr0,\tRSVD0,\t\tSOC_THERM_OC4,\t\tRSVD2,\t\tRSVD3,\t\t0x1f000,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio62_pr1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f008,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio63_pr2,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f010,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio64_pr3,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f018,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio65_pr4,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f020,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio66_pr5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f028,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio67_pr6,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f030,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio68_pr7,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1f038,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi3_miso_pa4,\t\tSPI3_DIN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd000,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi1_cs0_pb3,\t\tSPI1_CS0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd008,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi3_cs0_pa6,\t\tSPI3_CS0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd010,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi1_miso_pb1,\t\tSPI1_DIN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd018,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi3_cs1_pa7,\t\tSPI3_CS1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd020,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi1_sck_pb0,\t\tSPI1_SCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd028,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi3_sck_pa3,\t\tSPI3_SCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd030,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi1_cs1_pb4,\t\tSPI1_CS1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd038,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi1_mosi_pb2,\t\tSPI1_DOUT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd040,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi3_mosi_pa5,\t\tSPI3_DOUT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd048,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gpu_pwr_req_pa0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd050,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gp_pwm5_pa1,\t\tGP_PWM5,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd058,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gp_pwm6_pa2,\t\tGP_PWM6,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xd060,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(extperiph2_clk_pc3,\tEXTPERIPH2_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0000,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(extperiph1_clk_pc2,\tEXTPERIPH1_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0008,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(cam_i2c_sda_pc5,\tI2C3_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0010,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(cam_i2c_scl_pc4,\tI2C3_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0018,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio23_pc6,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0020,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio24_pc7,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0028,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio27_pd0,\tRSVD0,\t\tGP_PWM8,\t\tRSVD2,\t\tRSVD3,\t\t0x0040,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio29_pd2,\tRSVD0,\t\tNV_THERM_FAN_TACH0,\tRSVD2,\t\tRSVD3,\t\t0x0050,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio32_pd4,\tEXTPERIPH4_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0068,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio33_pd3,\tEXTPERIPH3_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0070,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio35_pd5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0078,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio37_pd6,\tDMIC2_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0080,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio56_pd7,\tDMIC2_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0088,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio55_pd1,\tRSVD0,\t\tWDT_RESET_OUTA,\t\tRSVD2,\t\tRSVD3,\t\t0x0090,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart1_cts_pe3,\t\tUARTA_CTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x0098,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart1_rts_pe2,\t\tUARTA_RTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x00a0,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart1_rx_pe1,\t\tUARTA_RXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x00a8,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart1_tx_pe0,\t\tUARTA_TXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x00b0,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwr_i2c_scl_pc0,\tI2C5_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x00b8,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwr_i2c_sda_pc1,\tI2C5_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x00c0,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(cpu_pwr_req_ph4,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4000,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart4_cts_pg5,\t\tUARTD_CTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4008,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart4_rts_pg4,\t\tUARTD_RTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4010,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart4_rx_pg3,\t\tUARTD_RXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4018,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart4_tx_pg2,\t\tUARTD_TXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4020,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen1_i2c_scl_ph2,\tI2C1_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4028,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen1_i2c_sda_ph3,\tI2C1_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4030,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio20_pf6,\tSDMMC1_CD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4038,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio21_pf7,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4040,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio22_pg0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4048,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio13_pf0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4050,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio14_pf1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4058,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio15_pf2,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4060,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio16_pf3,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4068,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio17_pf4,\tRSVD0,\t\tCCLA_LA_TRIGGER_MUX,\tRSVD2,\t\tRSVD3,\t\t0x4070,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio18_pf5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4078,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio41_pg6,\tI2S2_SCLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4088,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio42_pg7,\tI2S2_SDATA_OUT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4090,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio43_ph0,\tI2S2_SDATA_IN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x4098,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio44_ph1,\tI2S2_LRCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x40a0,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio06_pg1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x40a8,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio07_ph5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x40b0,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap4_sclk_pp4,\t\tI2S4_SCLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2000,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap4_dout_pp5,\t\tI2S4_SDATA_OUT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2008,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap4_din_pp6,\t\tI2S4_SDATA_IN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2010,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap4_fs_pp7,\t\tI2S4_LRCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2018,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio167_pp0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2040,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio168_pp1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2048,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio169_pp2,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2050,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio170_pp3,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2058,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio171_pq0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2060,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio172_pq1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2068,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio173_pq2,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x2070,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio45_pk0,\tI2S1_SCLK,\tDSPK1_DAT,\t\tDMIC3_CLK,\tRSVD3,\t\t0x18000,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio46_pk1,\tI2S1_SDATA_OUT,\tDSPK1_CLK,\t\tDMIC3_DAT,\tRSVD3,\t\t0x18008,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio47_pk2,\tI2S1_SDATA_IN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18010,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio48_pk3,\tI2S1_LRCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18018,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio57_pj4,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tSDMMC1_WP,\t0x18020,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio58_pj5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18028,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio59_pj6,\tAUD_MCLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18030,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio60_pj7,\tRSVD0,\t\tNV_THERM_FAN_TACH1,\tRSVD2,\t\tRSVD3,\t\t0x18038,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap3_fs_pj3,\t\tI2S3_LRCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18060,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap3_clk_pj0,\t\tI2S3_SCLK,\tDSPK0_DAT,\t\tDMIC4_CLK,\tRSVD3,\t\t0x18068,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap3_din_pj2,\t\tI2S3_SDATA_IN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x18070,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dap3_dout_pj1,\t\tI2S3_SDATA_OUT,\tDSPK0_CLK,\t\tDMIC4_DAT,\tRSVD3,\t\t0x18078,\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l2_clkreq_n_pw4,\tPE2_CLKREQ_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7000,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_wake_n_px0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7008,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l1_clkreq_n_pw2,\tPE1_CLKREQ_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7010,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l1_rst_n_pw3,\tPE1_RST_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7018,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l0_clkreq_n_pw0,\tPE0_CLKREQ_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7020,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l0_rst_n_pw1,\tPE0_RST_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7028,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l2_rst_n_pw5,\tPE2_RST_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7030,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l3_clkreq_n_pw6,\tPE3_CLKREQ_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7038,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pex_l3_rst_n_pw7,\tPE3_RST_L,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7040,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dp_aux_ch0_hpd_px1,\tDP_AUX_CH0_HPD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x7048,\t\t0,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(qspi0_io0_pl1,\t\tQSPI0_IO0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb000,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\tPINGROUP(qspi0_io1_pl2,\t\tQSPI0_IO1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb008,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\tPINGROUP(qspi0_sck_pl0,\t\tQSPI0_SCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb010,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\tPINGROUP(qspi0_cs_n_pl3,\tQSPI0_CS_N,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb018,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio156_pm0,\tRSVD0,\t\tI2S5_SCLK,\t\tRSVD2,\t\tRSVD3,\t\t0xb020,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio155_pl7,\tRSVD0,\t\tI2S6_LRCK,\t\tRSVD2,\t\tRSVD3,\t\t0xb028,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio160_pm4,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb030,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio154_pl6,\tRSVD0,\t\tI2S6_SDATA_IN,\t\tRSVD2,\t\tRSVD3,\t\t0xb038,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio152_pl4,\tRSVD0,\t\tI2S6_SCLK,\t\tRSVD2,\t\tRSVD3,\t\t0xb040,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio153_pl5,\tRSVD0,\t\tI2S6_SDATA_OUT,\t\tRSVD2,\t\tRSVD3,\t\t0xb048,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio161_pm5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb050,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio162_pm6,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb058,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio159_pm3,\tRSVD0,\t\tI2S5_LRCK,\t\tRSVD2,\t\tRSVD3,\t\t0xb060,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio157_pm1,\tRSVD0,\t\tI2S5_SDATA_OUT,\t\tRSVD2,\t\tRSVD3,\t\t0xb068,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio158_pm2,\tRSVD0,\t\tI2S5_SDATA_IN,\t\tRSVD2,\t\tRSVD3,\t\t0xb070,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart7_cts_pn2,\t\tUARTG_CTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb078,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart7_rts_pn1,\t\tUARTG_RTS,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb080,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart7_tx_pm7,\t\tUARTG_TXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb088,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart7_rx_pn0,\t\tUARTG_RXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0xb090,\t\t0,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(sdmmc1_clk_pu0,\tSDMMC1_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x8000,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(sdmmc1_cmd_pu1,\tSDMMC1_CMD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x8008,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(sdmmc1_comp,\t\tSDMMC1_COMP,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x8010,\t\t0,\tN,\t-1,\t-1,\t-1,\t-1,\t-1,\t-1,\t-1),\n+\tPINGROUP(sdmmc1_dat3_pu5,\tSDMMC1_DAT3,\tSDMMC1_PE3_RST_L,\tRSVD2,\t\tRSVD3,\t\t0x8018,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(sdmmc1_dat2_pu4,\tSDMMC1_DAT2,\tSDMMC1_PE3_CLKREQ_L,\tRSVD2,\t\tRSVD3,\t\t0x8020,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(sdmmc1_dat1_pu3,\tSDMMC1_DAT1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x8028,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(sdmmc1_dat0_pu2,\tSDMMC1_DAT0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x8030,\t\t0,\tY,\t-1,\t5,\t6,\t-1,\t9,\t10,\t12),\n+\tPINGROUP(ufs0_rst_n_pv1,\tUFS0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11000,\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\tPINGROUP(ufs0_ref_clk_pv0,\tUFS0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11008,\t0,\tY,\t-1,\t5,\t6,\t-1,\t-1,\t10,\t12),\n+\n+};\n+\n+static const struct tegra_pingroup tegra238_aon_groups[] = {\n+\tPINGROUP(bootv_ctl_n_paa0,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1028,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio00_paa1,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10f0,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(vcomp_alert_paa2,\tSOC_THERM_OC1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1058,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwm1_paa3,\t\tGP_PWM1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11c0,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(batt_oc_paa4,\t\tSOC_THERM_OC2,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1020,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio04_paa5,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1140,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio25_paa6,\tRSVD0,\t\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1158,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio26_paa7,\tRSVD0,\t\tSOC_THERM_OC3,\t\tRSVD2,\t\tRSVD3,\t\t0x1160,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(hdmi_cec_pbb0,\t\tHDMI_CEC,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1060,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi2_sck_pcc0,\t\tSPI2_SCK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10b0,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi2_miso_pcc1,\tSPI2_DIN,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10b8,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi2_mosi_pcc2,\tSPI2_DOUT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1090,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi2_cs0_pcc3,\t\tSPI2_CS0,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10a0,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(spi2_cs1_pcc4,\t\tSPI2_CS1,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11c8,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart3_tx_pcc5,\t\tUARTC_TXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1078,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(uart3_rx_pcc6,\t\tUARTC_RXD,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1070,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen2_i2c_scl_pcc7,\tI2C2_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1098,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen2_i2c_sda_pdd0,\tI2C2_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x10a8,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen8_i2c_scl_pdd1,\tI2C8_CLK,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1088,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(gen8_i2c_sda_pdd2,\tI2C8_DAT,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x1080,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(touch_clk_pdd3,\tGP_PWM4,\tTOUCH_CLK,\t\tRSVD2,\t\tRSVD3,\t\t0x1068,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dmic1_clk_pdd4,\tDMIC1_CLK,\tRSVD1,\t\t\tDMIC5_CLK,\tRSVD3,\t\t0x11d0,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(dmic1_dat_pdd5,\tDMIC1_DAT,\tRSVD1,\t\t\tDMIC5_DAT,\tRSVD3,\t\t0x11d8,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(soc_gpio19_pdd6,\tRSVD0,\t\tWDT_RESET_OUTB,\t\tRSVD2,\t\tRSVD3,\t\t0x10f8,\t\t1,\tY,\t-1,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwm2_pdd7,\t\tGP_PWM2,\tLED_BLINK,\t\tRSVD2,\t\tRSVD3,\t\t0x11b0,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwm3_pee0,\t\tGP_PWM3,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11b8,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+\tPINGROUP(pwm7_pee1,\t\tGP_PWM7,\tRSVD1,\t\t\tRSVD2,\t\tRSVD3,\t\t0x11a8,\t\t1,\tY,\t5,\t7,\t6,\t8,\t-1,\t10,\t12),\n+};\n+\n+static const struct tegra_pinctrl_soc_data tegra238_pinctrl_aon = {\n+\t.pins = tegra238_aon_pins,\n+\t.npins = ARRAY_SIZE(tegra238_aon_pins),\n+\t.functions = tegra238_functions,\n+\t.nfunctions = ARRAY_SIZE(tegra238_functions),\n+\t.groups = tegra238_aon_groups,\n+\t.ngroups = ARRAY_SIZE(tegra238_aon_groups),\n+\t.hsm_in_mux = false,\n+\t.schmitt_in_mux = true,\n+\t.drvtype_in_mux = true,\n+\t.sfsel_in_mux = true,\n+};\n+\n+static const struct tegra_pinctrl_soc_data tegra238_pinctrl = {\n+\t.pins = tegra238_pins,\n+\t.npins = ARRAY_SIZE(tegra238_pins),\n+\t.functions = tegra238_functions,\n+\t.nfunctions = ARRAY_SIZE(tegra238_functions),\n+\t.groups = tegra238_groups,\n+\t.ngroups = ARRAY_SIZE(tegra238_groups),\n+\t.hsm_in_mux = false,\n+\t.schmitt_in_mux = true,\n+\t.drvtype_in_mux = true,\n+\t.sfsel_in_mux = true,\n+};\n+\n+static int tegra238_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tconst struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);\n+\n+\treturn tegra_pinctrl_probe(pdev, soc);\n+}\n+\n+static const struct of_device_id tegra238_pinctrl_of_match[] = {\n+\t{ .compatible = \"nvidia,tegra238-pinmux\", .data = &tegra238_pinctrl },\n+\t{ .compatible = \"nvidia,tegra238-pinmux-aon\", .data = &tegra238_pinctrl_aon },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, tegra238_pinctrl_of_match);\n+\n+static struct platform_driver tegra238_pinctrl_driver = {\n+\t.driver = {\n+\t\t.name = \"tegra238-pinctrl\",\n+\t\t.of_match_table = tegra238_pinctrl_of_match,\n+\t},\n+\t.probe = tegra238_pinctrl_probe,\n+};\n+\n+static int __init tegra238_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&tegra238_pinctrl_driver);\n+}\n+module_init(tegra238_pinctrl_init);\n+\n+static void __exit tegra238_pinctrl_exit(void)\n+{\n+\tplatform_driver_unregister(&tegra238_pinctrl_driver);\n+}\n+module_exit(tegra238_pinctrl_exit);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"NVIDIA Corporation\");\n+MODULE_DESCRIPTION(\"NVIDIA Tegra238 pinctrl driver\");\n",
    "prefixes": [
        "3/6"
    ]
}