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GET /api/1.2/patches/2221422/?format=api
{ "id": 2221422, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2221422/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-7-2be1fb7cbbfc@hpe.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260408-hpe-gsc-upstream-v1-7-2be1fb7cbbfc@hpe.com>", "list_archive_url": null, "date": "2026-04-08T19:24:19", "name": "[7/9] board: hpe: Add GSC board support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "1b18d495814cbefeb1377770a1b4eacd2b4bc4b9", "submitter": { "id": 93099, "url": "http://patchwork.ozlabs.org/api/1.2/people/93099/?format=api", "name": "Jorge Cisneros", "email": "jorge.cisneros@hpe.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.2/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260408-hpe-gsc-upstream-v1-7-2be1fb7cbbfc@hpe.com/mbox/", "series": [ { "id": 499288, "url": "http://patchwork.ozlabs.org/api/1.2/series/499288/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499288", "date": "2026-04-08T19:24:17", "name": "arm: hpe: Add HPE GSC (Gen12) BMC SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499288/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221422/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221422/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=cc\n :content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pps0720; bh=nM\n DILvt0ap3A/KFQE4aYICtSG4LXPBStE3zXmjv573s=; b=Lc9UnyOd1xCaNiotJN\n Gxrgkss2/SzitoDdmD40s4m0mXcTmU/kIPfH8MI18iK53zCupTnOOawhflnp7xO1\n s+DZXATs7KxhloEtf4sYFNbGXKgV4uHKQd8US0ZxLyDwQpr7Ihpb02T0yhNZnXTr\n ZkQEzhvspLzIqIPDYgteSCPi9Ibbbjtv/v4pMGoLmRkKbNVSySUS4sWpVa+LpBkY\n bMOhuiFxwplNAixUzF07FAXyxtMkxLg309f5B/1jAwY1bH5NvMk2Ik24QW/Nt1kt\n ZkQSMZnNWOIoUvUY3PnexeixNW2aMc5gtBP9PS66PR0DlWzHcyYJPSkYUzXDfbGO\n SryQ==", "From": "Jorge Cisneros <jorge.cisneros@hpe.com>", "Date": "Wed, 08 Apr 2026 19:24:19 +0000", "Subject": "[PATCH 7/9] board: hpe: Add GSC board support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260408-hpe-gsc-upstream-v1-7-2be1fb7cbbfc@hpe.com>", "References": "<20260408-hpe-gsc-upstream-v1-0-2be1fb7cbbfc@hpe.com>", "In-Reply-To": "<20260408-hpe-gsc-upstream-v1-0-2be1fb7cbbfc@hpe.com>", "To": "u-boot@lists.denx.de", "Cc": "Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>,\n Tom Rini <trini@konsulko.com>, Jean-Marie Verdun <verdun@hpe.com>,\n Nick Hawkins <nick.hawkins@hpe.com>,\n Casey Connolly <casey.connolly@linaro.org>, Anshul Dalal <anshuld@ti.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>, Peng Fan <peng.fan@nxp.com>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,\n Tingting Meng <tingting.meng@altera.com>, Alice Guo <alice.guo@nxp.com>,\n Quentin Schulz <quentin.schulz@cherry.de>,\n Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Tony Dinh <mibodhi@gmail.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Stefan Roese <stefan.roese@mailbox.org>,\n Svyatoslav Ryhel <clamor95@gmail.com>,\n Patrice Chotard <patrice.chotard@foss.st.com>,\n Mattijs Korpershoek <mkorpershoek@kernel.org>,\n Shmuel Leib Melamud <smelamud@redhat.com>,\n Lukasz Majewski <lukma@nabladev.com>,\n Sumit Garg <sumit.garg@oss.qualcomm.com>,\n Chen-Yu Tsai <wens@kernel.org>, Justin Klaassen <justin@tidylabs.net>,\n Neha Malcom Francis <n-francis@ti.com>,\n Jamie Gibbons <jamie.gibbons@microchip.com>,\n Leo Yu-Chi Liang <ycliang@andestech.com>,\n Jerome Forissier <jerome.forissier@arm.com>,\n Simon Glass <sjg@chromium.org>,\n Neil Armstrong <neil.armstrong@linaro.org>, Yao Zi <me@ziyao.cc>,\n Kuan-Wei Chiu <visitorckw@gmail.com>,\n \"Kory Maincent (TI.com)\" <kory.maincent@bootlin.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Philip Molloy <philip.molloy@analog.com>,\n Jorge Cisneros <jorge.cisneros@hpe.com>", "X-Mailer": "b4 0.15.1", "X-Proofpoint-ORIG-GUID": "RuVtBhODG7VE1fZIfz9BZPXRAvXqHHz3", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA4MDE4MSBTYWx0ZWRfX4e5yzxLH7VO9\n hU0Eevy4gC2HzLtBXy6lTlWmuSrZJQ1FWxmw2jDclGuD6ec6JVF/GQuDQmTx7+XmchdbBDMsmB1\n raRm5OmR+ifjUWYfUj6Im+qvvkXnIvLTazSxLzy2GcbukTr3979tWEWUeROUeoPIhNowdMButmo\n 1aSAuSaBfj+Fu1HsMQ7PUrTZ92CSOkTUDUGm6DnDUgXO+q9VuIh2enHDYr+DOsSvD0Xi42RKKIg\n fWfvTvsO5yIQhXAMnGjU/ryE8VOBVpCQyZ367x+7W6WddWCSXsaClKbiWboMhPeVEhAmcEIen9r\n 6br1p7yAIXbVRAJZ3lagAtKKMzj/PN9UiRsxR4KzIjRbn21HCt1fy+2xhyo9n9VaW9SnClDzLbY\n xcY1HzpFtLrbahoemv/5W11ALdWcOTl318njlQAVpEapePXusbHhgIuYUz28uHASEOPzxGILgew\n kEIGG1OsLbwBxuqBRzw==", "X-Proofpoint-GUID": "RuVtBhODG7VE1fZIfz9BZPXRAvXqHHz3", "X-Authority-Analysis": "v=2.4 cv=S9HpBosP c=1 sm=1 tr=0 ts=69d6ab69 cx=c_pps\n a=A+SOMQ4XYIH4HgQ50p3F5Q==:117 a=A+SOMQ4XYIH4HgQ50p3F5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gQcMVamqm3wCPoSYhaRC:22 a=6_mrDcixewTG61oOsKN3:22 a=MvuuwTCpAAAA:8\n a=a6TSiJCG5VpFgIC85-cA:9 a=QEXdDO2ut3YA:10", "X-HPE-SCL": "-1", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_05,2026-04-08_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0\n malwarescore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080181", "X-Mailman-Approved-At": "Thu, 09 Apr 2026 15:00:51 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add board support for the HPE GSC (Gen Server Controller), the BMC\nSoC used in HPE Gen12 ProLiant and Synergy servers.\n\nBoard files include:\n- gsc_board.c: Board init, DRAM sizing from Denali memory controller,\n MAC address provisioning from memory-mapped EEPROM, and FDT fixups\n for network configuration based on CPLD xregisters\n- common-phy.c: Shared Ethernet/DisplayPort PHY initialization with\n configurable transmitter amplitude and de-emphasis\n- server_id.c: Custom command to read server identification from CPLD\n- gsc.env: Default SPI flash boot environment\n- gsc.h: Board configuration header with GICv3 and spin-table addresses\n\nSigned-off-by: Jorge Cisneros <jorge.cisneros@hpe.com>\n---\n board/hpe/gsc/Makefile | 3 +\n board/hpe/gsc/common-phy-wrapper-addresses.h | 86 +++++\n board/hpe/gsc/common-phy.c | 296 +++++++++++++++\n board/hpe/gsc/common-phy.h | 8 +\n board/hpe/gsc/gsc.env | 9 +\n board/hpe/gsc/gsc_board.c | 538 +++++++++++++++++++++++++++\n board/hpe/gsc/server_id.c | 51 +++\n include/configs/gsc.h | 25 ++\n 8 files changed, 1016 insertions(+)", "diff": "diff --git a/board/hpe/gsc/Makefile b/board/hpe/gsc/Makefile\nnew file mode 100644\nindex 00000000000..bc14c9d3bbf\n--- /dev/null\n+++ b/board/hpe/gsc/Makefile\n@@ -0,0 +1,3 @@\n+obj-y += gsc_board.o\n+obj-y += common-phy.o\n+obj-y += server_id.o\ndiff --git a/board/hpe/gsc/common-phy-wrapper-addresses.h b/board/hpe/gsc/common-phy-wrapper-addresses.h\nnew file mode 100644\nindex 00000000000..50bacd756f2\n--- /dev/null\n+++ b/board/hpe/gsc/common-phy-wrapper-addresses.h\n@@ -0,0 +1,86 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/* Copyright (C) 2022-2025 Hewlett-Packard Enterprise Development Company, L.P. */\n+\n+#ifndef _COMMON_PHY_WRAPPER_ADDRESSES_H\n+#define _COMMON_PHY_WRAPPER_ADDRESSES_H\n+\n+#define kWRAP_CDB_ENABLE\t\t0x8018\n+#define kWRAP_CDB_BUSSEL\t\t0x801c\n+#define kWRAP_CDB_ACC_OK\t\t0x8020\n+#define kWRAP_CDB_REG_INIT_END\t\t0x8024\n+\n+#define kWRAP_PHY_REFCLK_ACTIVE\t\t0x803c\n+#define kWRAP_PHY_CONFIG_RSTN\t\t0x8040\n+#define kWRAP_PHY_CMN_READY\t\t0x8044\n+#define kWRAP_PHY_LANE_EN_BITS\t\t0x8048\n+#define kWRAP_PHY_LANE_RSTN_BITS\t0x804c\n+\n+#define kWRAP_PHY_PLL0_ENABLE\t\t0x8050\n+#define kWRAP_PHY_PLL0_STATUS\t\t0x8054\n+\n+#define kWRAP_PHY_PLL1_ENABLE\t\t0x8058\n+#define kWRAP_PHY_PLL1_STATUS\t\t0x805c\n+\n+#define kWRAP_PHY_DP_LANE_MODE\t\t0x8060\n+#define kWRAP_PHY_DP_LANESET_READY\t0x8064\n+#define kWRAP_LANE_ELEC_IDLE_BITS\t0x8070\n+#define kWRAP_DP_DUAL_MODE_ENABLE\t0x8074\n+#define kWRAP_PHY_DP_LINK_RATE\t\t0x8078\n+#define kWRAP_DISABLE_AUTO_RXLINK\t0x807c\n+\n+#define kWRAP_TX_DEEMPH_LANE0\t\t0x8080\n+#define kWRAP_TX_DEEMPH_LANE1\t\t0x8084\n+#define kWRAP_TX_DEEMPH_LANE2\t\t0x8088\n+#define kWRAP_TX_DEEMPH_LANE3\t\t0x808c\n+\n+#define kWRAP_TX_VMARGIN_LANE0\t\t0x8090\n+#define kWRAP_TX_VMARGIN_LANE1\t\t0x8094\n+#define kWRAP_TX_VMARGIN_LANE2\t\t0x8098\n+#define kWRAP_TX_VMARGIN_LANE3\t\t0x809c\n+\n+#define kWRAP_XCVR_PLLCLK0_ENABLE\t0x80a0\n+#define kWRAP_XCVR_PLLCLK1_ENABLE\t0x80a4\n+#define kWRAP_XCVR_PLLCLK2_ENABLE\t0x80a8\n+#define kWRAP_XCVR_PLLCLK3_ENABLE\t0x80ac\n+\n+#define kWRAP_XCVR_PLLCLK0_EN_ACK\t0x80b0\n+#define kWRAP_XCVR_PLLCLK1_EN_ACK\t0x80b4\n+#define kWRAP_XCVR_PLLCLK2_EN_ACK\t0x80b8\n+#define kWRAP_XCVR_PLLCLK3_EN_ACK\t0x80bc\n+\n+#define kWRAP_XCVR_RATE_CHNG0_REQ\t0x80c0\n+#define kWRAP_XCVR_RATE_CHNG1_REQ\t0x80c4\n+#define kWRAP_XCVR_RATE_CHNG2_REQ\t0x80c8\n+#define kWRAP_XCVR_RATE_CHNG3_REQ\t0x80cc\n+\n+#define kWRAP_XCVR_RATE_CHNG0_ACK\t0x80d0\n+#define kWRAP_XCVR_RATE_CHNG1_ACK\t0x80d4\n+#define kWRAP_XCVR_RATE_CHNG2_ACK\t0x80d8\n+#define kWRAP_XCVR_RATE_CHNG3_ACK\t0x80dc\n+\n+#define kWRAP_XCVR_MODE_LANE0\t\t0x80e0\n+#define kWRAP_XCVR_MODE_LANE1\t\t0x80e4\n+#define kWRAP_XCVR_MODE_LANE2\t\t0x80e8\n+#define kWRAP_XCVR_MODE_LANE3\t\t0x80ec\n+\n+#define kWRAP_PHY_RX_DATA_ENABLE\t0x80f0\n+#define kWRAP_PHY_TX_DATA_ENABLE\t0x80f4\n+\n+#define kWRAP_PHY_XCVR0_SCANIN0\t0x8100\n+#define kWRAP_PHY_XCVR0_SCANIN1\t0x8104\n+#define kWRAP_PHY_XCVR1_SCANIN0\t0x8108\n+#define kWRAP_PHY_XCVR1_SCANIN1\t0x810c\n+#define kWRAP_PHY_XCVR2_SCANIN0\t0x8110\n+#define kWRAP_PHY_XCVR2_SCANIN1\t0x8114\n+#define kWRAP_PHY_XCVR3_SCANIN0\t0x8118\n+#define kWRAP_PHY_XCVR3_SCANIN1\t0x811c\n+#define kWRAP_PHY_XCVR0_SCANOUT0\t0x8120\n+#define kWRAP_PHY_XCVR0_SCANOUT1\t0x8124\n+#define kWRAP_PHY_XCVR1_SCANOUT0\t0x8128\n+#define kWRAP_PHY_XCVR1_SCANOUT1\t0x812c\n+#define kWRAP_PHY_XCVR2_SCANOUT0\t0x8130\n+#define kWRAP_PHY_XCVR2_SCANOUT1\t0x8134\n+#define kWRAP_PHY_XCVR3_SCANOUT0\t0x8138\n+#define kWRAP_PHY_XCVR3_SCANOUT1\t0x813c\n+\n+#endif /* _COMMON_PHY_WRAPPER_ADDRESSES_H */\ndiff --git a/board/hpe/gsc/common-phy.c b/board/hpe/gsc/common-phy.c\nnew file mode 100644\nindex 00000000000..c39653727e9\n--- /dev/null\n+++ b/board/hpe/gsc/common-phy.c\n@@ -0,0 +1,296 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/* Copyright (C) 2022-2025 Hewlett-Packard Enterprise Development Company, L.P. */\n+\n+#include <dm.h>\n+#include <asm/io.h>\n+#include <linux/delay.h>\n+\n+#include \"common-phy-wrapper-addresses.h\"\n+\n+#define DP_TX_BASE\t\t\t0xc0020000\n+#define PHY_PIP_CONFIG_REG_INDEX_ADDR\t0x0FC0\n+#define PHY_PIP_CONFIG_REG_DATA_ADDR\t0x0FC4\n+\n+/*\n+ * Xreg 0x39 Layout - Transmitter Amplitude\n+ *\n+ * Bits | Desc\n+ * 7 | Secondary Transmitter Disable\n+ * 6:4 | Secondary Transmitter Amplitude\n+ * 3 | Primary Transmitter Disable\n+ * 2:0 | Primary Transmitter Amplitude\n+ */\n+#define V_AMPLT_400\t\t0x4\n+#define V_AMPLT_600\t\t0x5\n+#define V_AMPLT_800\t\t0x6\n+#define V_AMPLT_945\t\t0x7\n+\n+/* Xreg 0x38 De-emphasis Levels */\n+#define DE_EMPH_0\t\t0x0\n+#define DE_EMPH_1\t\t0x1\n+#define DE_EMPH_2\t\t0x2\n+#define DE_EMPH_3\t\t0x3\n+\n+/* Xreg Mask and Shift */\n+#define V_AMPLT_MASK\t\t\t0x7\n+#define DE_EMPH_MASK\t\t\t0x3\n+#define DISABLE_MASK\t\t\t0x8\n+#define SECONDARY_SHIFT_V_AMPLT\t\t0x4\n+#define SECONDARY_SHIFT_DE_EMPH\t\t0x2\n+\n+static void common_phy_register_write(unsigned int reg, unsigned int data)\n+{\n+\twritel(reg, DP_TX_BASE + PHY_PIP_CONFIG_REG_INDEX_ADDR);\n+\twritel(data, DP_TX_BASE + PHY_PIP_CONFIG_REG_DATA_ADDR);\n+}\n+\n+static void common_phy_register_read(unsigned int reg, unsigned int *data)\n+{\n+\twritel(reg, DP_TX_BASE + PHY_PIP_CONFIG_REG_INDEX_ADDR);\n+\t*data = readl(DP_TX_BASE + PHY_PIP_CONFIG_REG_DATA_ADDR);\n+}\n+\n+static int poll_register(unsigned int reg, int value)\n+{\n+\tunsigned int data = 0;\n+\tint retry_cnt = 20;\n+\n+\twhile (retry_cnt > 0) {\n+\t\tcommon_phy_register_read(reg, &data);\n+\t\tif (data == value)\n+\t\t\treturn 0;\n+\t\tmdelay(1);\n+\t\tretry_cnt--;\n+\t}\n+\n+\tpr_err(\"CommonPhy: polling failed: reg=0x%x expected=0x%x got=0x%x\\n\",\n+\t reg, value, data);\n+\treturn -1;\n+}\n+\n+static void common_phy_get_deemph_and_vamplitude(unsigned int amplt,\n+\t\t\t\t\t\t unsigned int emph,\n+\t\t\t\t\t\t unsigned int *reg_amplt,\n+\t\t\t\t\t\t unsigned int *reg_emph)\n+{\n+\t/* Default: 400 mV, de-emphasis level 0 */\n+\t*reg_amplt = 0x00040404;\n+\t*reg_emph = 0x00000000;\n+\n+\tif (emph > DE_EMPH_3) {\n+\t\tpr_err(\"CommonPhy: invalid config: amplitude 0x%x, de-emph 0x%x\\n\",\n+\t\t amplt, emph);\n+\t\treturn;\n+\t}\n+\n+\tif (amplt == V_AMPLT_400) {\n+\t\tif (emph == DE_EMPH_0) {\n+\t\t\t*reg_amplt = 0x00040404;\n+\t\t\t*reg_emph = 0x00000000;\n+\t\t} else if (emph == DE_EMPH_1) {\n+\t\t\t*reg_amplt = 0x00030303;\n+\t\t\t*reg_emph = 0x00030404;\n+\t\t} else if (emph == DE_EMPH_2) {\n+\t\t\t*reg_amplt = 0x00010101;\n+\t\t\t*reg_emph = 0x00050606;\n+\t\t} else if (emph == DE_EMPH_3) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00060606;\n+\t\t}\n+\t} else if (amplt == V_AMPLT_600) {\n+\t\tif (emph == DE_EMPH_0) {\n+\t\t\t*reg_amplt = 0x00030303;\n+\t\t\t*reg_emph = 0x00000000;\n+\t\t} else if (emph == DE_EMPH_1) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00030404;\n+\t\t} else if (emph == DE_EMPH_2) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00050606;\n+\t\t} else if (emph == DE_EMPH_3) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00060606;\n+\t\t}\n+\t} else if (amplt == V_AMPLT_800) {\n+\t\tif (emph == DE_EMPH_0) {\n+\t\t\t*reg_amplt = 0x00040404;\n+\t\t\t*reg_emph = 0x00010101;\n+\t\t} else if (emph == DE_EMPH_1) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00030404;\n+\t\t} else if (emph == DE_EMPH_2) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00050606;\n+\t\t} else if (emph == DE_EMPH_3) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00060606;\n+\t\t}\n+\t} else if (amplt == V_AMPLT_945) {\n+\t\tif (emph == DE_EMPH_0) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00000000;\n+\t\t} else if (emph == DE_EMPH_1) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00030404;\n+\t\t} else if (emph == DE_EMPH_2) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00050606;\n+\t\t} else if (emph == DE_EMPH_3) {\n+\t\t\t*reg_amplt = 0x00000000;\n+\t\t\t*reg_emph = 0x00060606;\n+\t\t}\n+\t} else {\n+\t\tpr_err(\"CommonPhy: invalid config: amplitude 0x%x, de-emph 0x%x\\n\",\n+\t\t amplt, emph);\n+\t}\n+}\n+\n+/*\n+ * Power On Initialization of Common PHY.\n+ * Configures the shared PHY for Ethernet and Display Port operation.\n+ */\n+int common_phy_poweron_init(void)\n+{\n+\tunsigned int xreg_amplt, xreg_emph, emph, amplt;\n+\tunsigned int rstn_bits = 0x0F;\n+\n+\t/* 1. Clear registers to default un-initialized state */\n+\tcommon_phy_register_write(kWRAP_PHY_RX_DATA_ENABLE, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_TX_DATA_ENABLE, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_LANE_RSTN_BITS, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_LANE_EN_BITS, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_CONFIG_RSTN, 0x00);\n+\tcommon_phy_register_write(kWRAP_LANE_ELEC_IDLE_BITS, 0x0F);\n+\tcommon_phy_register_write(kWRAP_PHY_PLL0_ENABLE, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_PLL1_ENABLE, 0x00);\n+\tcommon_phy_register_write(kWRAP_CDB_BUSSEL, 0x00);\n+\tcommon_phy_register_write(kWRAP_CDB_REG_INIT_END, 0x00);\n+\tcommon_phy_register_write(kWRAP_PHY_DP_LANE_MODE, 0x00);\n+\tcommon_phy_register_write(kWRAP_DISABLE_AUTO_RXLINK, 0x01);\n+\tcommon_phy_register_write(kWRAP_XCVR_MODE_LANE0, 0x00);\n+\tcommon_phy_register_write(kWRAP_XCVR_MODE_LANE1, 0x00);\n+\tcommon_phy_register_write(kWRAP_XCVR_MODE_LANE2, 0x00);\n+\tcommon_phy_register_write(kWRAP_XCVR_MODE_LANE3, 0x00);\n+\n+\t/* 2. Release PHY lanes out of reset */\n+\tcommon_phy_register_write(kWRAP_PHY_CONFIG_RSTN, 0x01);\n+\n+\t/* 3. Poll for internal initialization completion */\n+\tif (poll_register(kWRAP_CDB_ACC_OK, 0x01) != 0) {\n+\t\tpr_err(\"CommonPhy: kWRAP_CDB_ACC_OK polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* 4. Additional PHY register modifications */\n+\tcommon_phy_register_write(kWRAP_CDB_BUSSEL, 0x01);\n+\tcommon_phy_register_write(kWRAP_CDB_ENABLE, 0x01);\n+\n+\t/* Set DP lanes for Dual Mode */\n+\tcommon_phy_register_write(0x4021, 0x00);\n+\tcommon_phy_register_write(0x4221, 0x00);\n+\n+\t/* RX Lane Fixes B0 */\n+\tcommon_phy_register_write(0x4026, 0x124A);\n+\tcommon_phy_register_write(0x4226, 0x124A);\n+\tcommon_phy_register_write(0x4226, 0x124A);\n+\tcommon_phy_register_write(0x4626, 0x124A);\n+\n+\tcommon_phy_register_write(kWRAP_CDB_BUSSEL, 0x00);\n+\tcommon_phy_register_write(kWRAP_CDB_ENABLE, 0x00);\n+\n+\t/* 5. Set PHY initialization complete */\n+\tcommon_phy_register_write(kWRAP_CDB_REG_INIT_END, 0x01);\n+\n+\t/* 6. Enable PLL 0 and PLL 1 */\n+\tcommon_phy_register_write(kWRAP_PHY_PLL0_ENABLE, 0x01);\n+\tcommon_phy_register_write(kWRAP_PHY_PLL1_ENABLE, 0x01);\n+\n+\t/* 7. Program vswing/pre-emphasis for DP lanes 0 and 1 */\n+\tcommon_phy_register_write(kWRAP_TX_VMARGIN_LANE0, 0x00040404);\n+\tcommon_phy_register_write(kWRAP_TX_VMARGIN_LANE1, 0x00040404);\n+\tcommon_phy_register_write(kWRAP_TX_DEEMPH_LANE0, 0x00000000);\n+\tcommon_phy_register_write(kWRAP_TX_DEEMPH_LANE1, 0x00000000);\n+\n+\t/* 8. Program vswing/pre-emphasis for Ethernet lanes 2 and 3 */\n+\txreg_amplt = readb(0xd1000039);\n+\txreg_emph = readb(0xd1000038);\n+\n+\tdebug(\"CommonPhy: amplitude=0x%x de-emph=0x%x\\n\",\n+\t xreg_amplt, xreg_emph);\n+\n+\t/* Primary transmitter */\n+\tif ((xreg_amplt & DISABLE_MASK) == 0) {\n+\t\tdebug(\"CommonPhy: configuring primary transmitter\\n\");\n+\t\tcommon_phy_get_deemph_and_vamplitude(\n+\t\t\txreg_amplt & V_AMPLT_MASK,\n+\t\t\txreg_emph & DE_EMPH_MASK,\n+\t\t\t&lt, &emph);\n+\t\tcommon_phy_register_write(kWRAP_TX_VMARGIN_LANE2, amplt);\n+\t\tcommon_phy_register_write(kWRAP_TX_DEEMPH_LANE2, emph);\n+\t} else {\n+\t\tdebug(\"CommonPhy: primary transmitter disabled\\n\");\n+\t\trstn_bits &= 0x0B;\n+\t}\n+\n+\t/* Secondary transmitter */\n+\tif (((xreg_amplt >> SECONDARY_SHIFT_V_AMPLT) & DISABLE_MASK) == 0) {\n+\t\tdebug(\"CommonPhy: configuring secondary transmitter\\n\");\n+\t\tcommon_phy_get_deemph_and_vamplitude(\n+\t\t\t(xreg_amplt >> SECONDARY_SHIFT_V_AMPLT) & V_AMPLT_MASK,\n+\t\t\t(xreg_emph >> SECONDARY_SHIFT_DE_EMPH) & DE_EMPH_MASK,\n+\t\t\t&lt, &emph);\n+\t\tcommon_phy_register_write(kWRAP_TX_VMARGIN_LANE3, amplt);\n+\t\tcommon_phy_register_write(kWRAP_TX_DEEMPH_LANE3, emph);\n+\t} else {\n+\t\tdebug(\"CommonPhy: secondary transmitter disabled\\n\");\n+\t\trstn_bits &= 0x07;\n+\t}\n+\n+\t/* 9. Take lanes out of Electrical Idle */\n+\tcommon_phy_register_write(kWRAP_LANE_ELEC_IDLE_BITS, 0x0);\n+\n+\t/* 10. Enable PLL Clocks */\n+\tcommon_phy_register_write(kWRAP_XCVR_PLLCLK0_ENABLE, 0x01);\n+\tcommon_phy_register_write(kWRAP_XCVR_PLLCLK2_ENABLE, 0x01);\n+\tcommon_phy_register_write(kWRAP_XCVR_PLLCLK3_ENABLE, 0x01);\n+\n+\t/* 11. Release lane resets */\n+\tcommon_phy_register_write(kWRAP_PHY_LANE_RSTN_BITS, rstn_bits);\n+\n+\t/* 12. Enable Lanes (DisplayPort only) */\n+\tcommon_phy_register_write(kWRAP_PHY_LANE_EN_BITS, 0x0F);\n+\n+\t/* 13. Poll for Common Ready */\n+\tif (poll_register(kWRAP_PHY_CMN_READY, 0x01) != 0) {\n+\t\tpr_err(\"CommonPhy: kWRAP_PHY_CMN_READY polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* 14. Poll for PLL status */\n+\tif (poll_register(kWRAP_XCVR_PLLCLK0_EN_ACK, 0x01) != 0) {\n+\t\tpr_err(\"CommonPhy: PLLCLK0_EN_ACK polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (poll_register(kWRAP_XCVR_PLLCLK1_EN_ACK, 0x01) != 0) {\n+\t\tpr_err(\"CommonPhy: PLLCLK1_EN_ACK polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (poll_register(kWRAP_XCVR_PLLCLK2_EN_ACK, 0x01) != 0) {\n+\t\tpr_err(\"CommonPhy: PLLCLK2_EN_ACK polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* 15. Poll for Lanes ready */\n+\tif (poll_register(kWRAP_PHY_DP_LANESET_READY, 0x0F) != 0) {\n+\t\tpr_err(\"CommonPhy: DP_LANESET_READY polling failed\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* 16. Enable TX data flow */\n+\tcommon_phy_register_write(kWRAP_PHY_TX_DATA_ENABLE, 0x01);\n+\n+\t/* 17. Set DP Link Rate to 1.62 Gbps */\n+\tcommon_phy_register_write(kWRAP_PHY_DP_LINK_RATE, 0x6);\n+\n+\treturn 0;\n+}\ndiff --git a/board/hpe/gsc/common-phy.h b/board/hpe/gsc/common-phy.h\nnew file mode 100644\nindex 00000000000..bb41ea21ffa\n--- /dev/null\n+++ b/board/hpe/gsc/common-phy.h\n@@ -0,0 +1,8 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef _COMMON_PHY_H\n+#define _COMMON_PHY_H\n+\n+int common_phy_poweron_init(void);\n+\n+#endif /* _COMMON_PHY_H */\ndiff --git a/board/hpe/gsc/gsc.env b/board/hpe/gsc/gsc.env\nnew file mode 100644\nindex 00000000000..9723c30ba40\n--- /dev/null\n+++ b/board/hpe/gsc/gsc.env\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+loadfit=sf probe;sf read 0x2000000 0x1a0000 0xa00000;\n+recover_cmd=bootm 0xfc1a0000;\n+spiboot=run loadfit; saveenv; bootm 0x2000000;\n+run recover_cmd;\n+while itest 0 < 1; do\n+\techo KERNEL BOOT FAILURE!;\n+done;\ndiff --git a/board/hpe/gsc/gsc_board.c b/board/hpe/gsc/gsc_board.c\nnew file mode 100644\nindex 00000000000..bc86fd07485\n--- /dev/null\n+++ b/board/hpe/gsc/gsc_board.c\n@@ -0,0 +1,538 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+// Copyright (C) 2019-2025 Hewlett-Packard Enterprise Development Company, L.P.\n+\n+#include <dm.h>\n+#include <env.h>\n+#include <ram.h>\n+#include <timer.h>\n+#include <asm/io.h>\n+#include <linux/err.h>\n+#include <linux/delay.h>\n+#include <dm/uclass.h>\n+#include <console.h>\n+#include <asm/armv8/mmu.h>\n+#include <fdt_support.h>\n+#include <phy.h>\n+#include <net.h>\n+#include <i2c_eeprom.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define ARCH_TIMER_CNTCR_REG\t0xc0034000\n+#define ARCH_TIMER_CNTFID0\t0xc0034020\n+#define ARCH_TIMER_FREQUENCY\t50000000\n+#define ARCH_TIMER_CNTCR_ENABLE\tBIT(0)\n+#define ARCH_TIMER_CNTCR_HDBG\tBIT(1)\n+\n+#define DEFAULT_RESERVED_MEMORY_SIZE\t(0x300000u)\n+#define DEFAULT_VIDEO_RAM_SIZE\t\t(0x1000000u)\n+#define DENALI_ROW_DIFF\t\t\t(0xCEFE219C)\n+#define DENALI_ECC_ENABLE_DISABLE\t(0xCEFE2134)\n+#define DENALI_NON_ECC_REGION_ENABLED\t(0xCEFE2170)\n+#define DENALI_REG_NONECC_REGION_ONE\t(0xCEFE2168)\n+#define DENALI_REG_NONECC_REGION_TWO\t(0xCEFE216C)\n+#define VMEMOFF_ADDRESS\t\t\t(0xc000001c)\n+#define VIDEOMEM_ARRAY_SIZE\t\t(7u)\n+#define V_EEPROM_RO_START\t\t(128)\n+#define V_EEPROM_RO_MAC0\t\t(V_EEPROM_RO_START + 4)\n+#define V_EEPROM_RO_MAC1\t\t(V_EEPROM_RO_START + 10)\n+#define V_EEPROM_RO_SN\t\t\t(1)\n+#define V_EEPROM_RO_PN\t\t\t(109)\n+#define V_EEPROM_RO_PCA_SN\t\t(144)\n+#define V_EEPROM_RO_PCA_PN\t\t(160)\n+#define SSTRAP\t\t\t\t0xc0000af0\n+#define MEMID_BYTE_4\t\t\t0xd1e10004\n+#define MEMCGF_ADDRESS\t\t\t0xc0000024\n+\n+#define GSC_MACB0\t\t\"/ahb/ethernet@c0004000/\"\n+#define GSC_MACB2\t\t\"/ahb/ethernet@c0006000/\"\n+#define GSC_MACB0_ETHERNET_PHY\t\"/ahb/ethernet@c0004000/ethernet-phy@0/\"\n+#define GSC_MACB2_ETHERNET_PHY\t\"/ahb/ethernet@c0006000/ethernet-phy@0/\"\n+#define GSC_I3C_HUB_PORT_0\t\"/ahb/i3c@c0003300/hub@0,0/target-port@0/\"\n+#define GSC_I3C_HUB_PORT_1\t\"/ahb/i3c@c0003300/hub@0,0/target-port@1/\"\n+#define GSC_I3C_HUB_PORT_2\t\"/ahb/i3c@c0003300/hub@0,0/target-port@2/\"\n+#define GSC_I3C_HUB_PORT_3\t\"/ahb/i3c@c0003300/hub@0,0/target-port@3/\"\n+\n+/* Xregister Network Configuration Definitions v0x25 */\n+#define GSC_PRIMARY_SECONDARY_CFG\t0xd1000038\n+#define GSC_SECONDARY_MAC_SHIFT\t\t4\n+#define GSC_SECONDARY_MAC_MASK\t\t0x30\n+#define GSC_PRIMARY_MAC_SHIFT\t\t6\n+#define GSC_PRIMARY_MAC_MASK\t\t0xc0\n+#define FAILOVER_SOFTSTRAP_MASK\t\t0x6000\n+#define GSC_PRIMARY_SECONDARY_PHY_TYPE\t0xd100003b\n+#define GSC_SECONDARY_TYPE_SHIFT\t1\n+#define GSC_SECONDARY_TYPE_MASK\t\t0x0E\n+#define GSC_PRIMARY_TYPE_SHIFT\t\t4\n+#define GSC_PRIMARY_TYPE_MASK\t\t0x30\n+#define GSC_PRIMARY_SPEED_DUPLEX\t0xd100003c\n+#define GSC_SECONDARY_SPEED_DUPLEX\t0xd100003d\n+#define GSC_DUPLEX_AUTO_MASK\t\t0x08\n+#define GSC_DUPLEX_FULL_MASK\t\t0x04\n+#define GSC_SPEED_AUTO_MASK\t\t0x80\n+#define GSC_SPEED_1000_MASK\t\t0x40\n+\n+#include \"common-phy.h\"\n+\n+static int get_eeprom_val(uint offset, u8 *v_ptr, size_t len)\n+{\n+\tstruct udevice *dev;\n+\tint ret;\n+\n+\tret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);\n+\tif (ret) {\n+\t\tdebug(\"%s Uclass_first_device_err %d\\n\", __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = i2c_eeprom_read(dev, offset, v_ptr, len);\n+\tif (ret) {\n+\t\tdebug(\"%s Read eeprom failure %d\\n\", __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int __ft_add_fixed_link(void *blob, int nodeoff)\n+{\n+\tint rc;\n+\n+\tnodeoff = fdt_add_subnode(blob, nodeoff, \"fixed-link\");\n+\tif (nodeoff < 0) {\n+\t\tpr_err(\"Failed to add fixed-link subnode %d\\n\", nodeoff);\n+\t\treturn nodeoff;\n+\t}\n+\n+\trc = fdt_setprop_u32(blob, nodeoff, \"speed\", 1000);\n+\tif (rc < 0) {\n+\t\tpr_err(\"Failed to set speed property: %d\\n\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trc = fdt_setprop(blob, nodeoff, \"full-duplex\", NULL, 0);\n+\tif (rc < 0) {\n+\t\tpr_err(\"Failed to set full-duplex property: %d\\n\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int set_vpd_val(void *blob, uint offset, u8 *val, size_t len,\n+\t\t char *name)\n+{\n+\tint ret, i;\n+\tsize_t str_len;\n+\tint actual_len = 0;\n+\n+\tret = get_eeprom_val(offset, val, len);\n+\tif (ret) {\n+\t\tpr_err(\"Failed to read %s from veeprom: %d\\n\", name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < len - 1; i++) {\n+\t\tif (val[i] == '\\0' || val[i] < 0x20 || val[i] > 0x7E) {\n+\t\t\tactual_len = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (actual_len == 0 && i == len - 1)\n+\t\tactual_len = len - 1;\n+\n+\tval[actual_len] = '\\0';\n+\tstr_len = actual_len + 1;\n+\n+\tret = fdt_setprop(blob, fdt_path_offset(blob, \"/\"), name, val, str_len);\n+\tif (ret < 0) {\n+\t\tpr_err(\"Failed to set %s in DTB: %s\\n\", name,\n+\t\t fdt_strerror(ret));\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ft_board_setup_vpd(void *blob, struct bd_info *bd)\n+{\n+\tif (IS_ENABLED(CONFIG_GSC_PATCH_KERNEL_DTS_VPD)) {\n+\t\tu8 val[16];\n+\n+\t\tset_vpd_val(blob, V_EEPROM_RO_SN, val, 16, \"sn\");\n+\t\tset_vpd_val(blob, V_EEPROM_RO_PN, val, 16, \"pn\");\n+\t\tset_vpd_val(blob, V_EEPROM_RO_PCA_SN, val, 16, \"serial-number\");\n+\t\tset_vpd_val(blob, V_EEPROM_RO_PCA_PN, val, 16, \"model\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ft_board_config_i3c_hub(void *blob, struct bd_info *bd)\n+{\n+\tstatic const char * const port_paths[] = {\n+\t\tGSC_I3C_HUB_PORT_0,\n+\t\tGSC_I3C_HUB_PORT_1,\n+\t\tGSC_I3C_HUB_PORT_2,\n+\t\tGSC_I3C_HUB_PORT_3,\n+\t};\n+\tu8 cpu;\n+\tint nodeoff, rc, i;\n+\n+\tif (!IS_ENABLED(CONFIG_GSC_I3C_HUB_DT))\n+\t\treturn 0;\n+\n+\tcpu = readb(MEMID_BYTE_4);\n+\tif (cpu == 0) {\n+\t\tpr_err(\"Error: CPU Presence = 0\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(port_paths); i++) {\n+\t\tif (cpu & BIT(i))\n+\t\t\tcontinue;\n+\n+\t\tnodeoff = fdt_path_offset(blob, port_paths[i]);\n+\t\tif (nodeoff < 0) {\n+\t\t\tpr_err(\"Failed to find I3C hub port %d\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\trc = fdt_del_node(blob, nodeoff);\n+\t\tif (rc < 0)\n+\t\t\tpr_err(\"Failed to delete I3C hub port %d: %d\\n\", i, rc);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\tint rc, nodeoff;\n+\tunsigned int tmp;\n+\tu8 val;\n+\tu8 mac2_is_primary = 0;\n+\n+\trc = ft_board_config_i3c_hub(blob, bd);\n+\tif (rc)\n+\t\tpr_err(\"I3C Hub DT Adjustment failed: %d\\n\", rc);\n+\n+\ttmp = readl(SSTRAP);\n+\n+\tif (tmp & FAILOVER_SOFTSTRAP_MASK) {\n+\t\tval = (readb(GSC_PRIMARY_SECONDARY_CFG) & GSC_PRIMARY_MAC_MASK)\n+\t\t\t\t>> GSC_PRIMARY_MAC_SHIFT;\n+\t\tif (val == 0x00) {\n+\t\t\tval = (readb(GSC_PRIMARY_SECONDARY_PHY_TYPE) &\n+\t\t\t\t\tGSC_PRIMARY_TYPE_MASK)\n+\t\t\t\t\t>> GSC_PRIMARY_TYPE_SHIFT;\n+\t\t\tif (val == 0x01) {\n+\t\t\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0);\n+\t\t\t\tif (nodeoff < 0) {\n+\t\t\t\t\tpr_err(\"Failed to find macb0 node\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\n+\t\t\t\trc = fdt_delprop(blob, nodeoff, \"phy-handle\");\n+\t\t\t\tif (rc < 0) {\n+\t\t\t\t\tpr_err(\"Failed to delete phy-handle\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\n+\t\t\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0_ETHERNET_PHY);\n+\t\t\t\tif (nodeoff < 0) {\n+\t\t\t\t\tpr_err(\"Failed to find macb0 phy node\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\n+\t\t\t\trc = fdt_del_node(blob, nodeoff);\n+\t\t\t\tif (rc < 0) {\n+\t\t\t\t\tpr_err(\"Failed to delete phy node\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tval = readb(GSC_PRIMARY_SPEED_DUPLEX);\n+\t\t\tif (val == (GSC_DUPLEX_FULL_MASK | GSC_SPEED_1000_MASK)) {\n+\t\t\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0);\n+\t\t\t\tif (nodeoff < 0) {\n+\t\t\t\t\tpr_err(\"Failed to find macb0 node\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\n+\t\t\t\trc = __ft_add_fixed_link(blob, nodeoff);\n+\t\t\t\tif (rc < 0) {\n+\t\t\t\t\tpr_err(\"Failed to add macb0 fixed-link\\n\");\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\trc = fdt_find_and_setprop(blob, GSC_MACB0, \"status\",\n+\t\t\t\t\t\t \"okay\", 6, 1);\n+\t\t\tif (rc < 0)\n+\t\t\t\tpr_err(\"Failed to set okay (%s)\\n\", GSC_MACB0);\n+\n+\t\t} else if (val == 0x02) {\n+\t\t\tmac2_is_primary = 1;\n+\t\t\trc = fdt_find_and_setprop(blob, GSC_MACB2, \"status\",\n+\t\t\t\t\t\t \"okay\", 6, 1);\n+\t\t\tif (rc < 0)\n+\t\t\t\tpr_err(\"Failed to set okay (%s)\\n\", GSC_MACB2);\n+\t\t}\n+\n+\t\tval = (readb(GSC_PRIMARY_SECONDARY_CFG) & GSC_SECONDARY_MAC_MASK)\n+\t\t\t\t>> GSC_SECONDARY_MAC_SHIFT;\n+\t\tif (val == 0x00) {\n+\t\t\tif (mac2_is_primary) {\n+\t\t\t\trc = fdt_find_and_setprop(blob, GSC_MACB0,\n+\t\t\t\t\t\t\t \"status\",\n+\t\t\t\t\t\t\t \"disabled\", 10, 1);\n+\t\t\t\tif (rc < 0)\n+\t\t\t\t\tpr_err(\"Failed to disable (%s)\\n\",\n+\t\t\t\t\t GSC_MACB0);\n+\t\t\t} else {\n+\t\t\t\tval = (readb(GSC_PRIMARY_SECONDARY_PHY_TYPE) &\n+\t\t\t\t\tGSC_SECONDARY_TYPE_MASK)\n+\t\t\t\t\t>> GSC_SECONDARY_TYPE_SHIFT;\n+\t\t\t\tif (val == 0x00) {\n+\t\t\t\t\trc = fdt_find_and_setprop(blob,\n+\t\t\t\t\t\t\t\t GSC_MACB2,\n+\t\t\t\t\t\t\t\t \"status\",\n+\t\t\t\t\t\t\t\t \"disabled\",\n+\t\t\t\t\t\t\t\t 10, 1);\n+\t\t\t\t\tif (rc < 0)\n+\t\t\t\t\t\tpr_err(\"Failed to disable (%s)\\n\",\n+\t\t\t\t\t\t GSC_MACB2);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\t/* Failover mode: configure 1000base-x */\n+\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0);\n+\t\tif (nodeoff < 0) {\n+\t\t\tpr_err(\"Failed to find macb0 node\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trc = fdt_delprop(blob, nodeoff, \"phy-handle\");\n+\t\tif (rc < 0) {\n+\t\t\tpr_err(\"Failed to delete phy-handle\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0_ETHERNET_PHY);\n+\t\tif (nodeoff < 0) {\n+\t\t\tpr_err(\"Failed to find macb0 phy node\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trc = fdt_del_node(blob, nodeoff);\n+\t\tif (rc < 0) {\n+\t\t\tpr_err(\"Failed to delete phy node\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trc = fdt_find_and_setprop(blob, GSC_MACB0, \"phy-mode\",\n+\t\t\t\t\t \"1000base-x\", 12, 0);\n+\t\tif (rc < 0) {\n+\t\t\tpr_err(\"Failed to set phy-mode\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tnodeoff = fdt_path_offset(blob, GSC_MACB0);\n+\t\tif (nodeoff < 0) {\n+\t\t\tpr_err(\"Failed to find macb0 node\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trc = __ft_add_fixed_link(blob, nodeoff);\n+\t\tif (rc < 0) {\n+\t\t\tpr_err(\"Failed to add macb0 fixed-link\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\trc = fdt_find_and_setprop(blob, GSC_MACB0, \"status\",\n+\t\t\t\t\t \"okay\", 6, 1);\n+\t\tif (rc < 0)\n+\t\t\tpr_err(\"Failed to set okay (%s)\\n\", GSC_MACB0);\n+\n+\t\trc = fdt_find_and_setprop(blob, GSC_MACB2, \"status\",\n+\t\t\t\t\t \"disabled\", 10, 1);\n+\t\tif (rc < 0)\n+\t\t\tpr_err(\"Failed to disable (%s)\\n\", GSC_MACB2);\n+\t}\n+\n+\tft_board_setup_vpd(blob, bd);\n+\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\t/* Apply runtime FDT changes to U-Boot's own device tree */\n+\tft_board_setup((void *)gd->fdt_blob, gd->bd);\n+\n+\treturn 0;\n+}\n+\n+static struct mm_region gsc_mem_map[] = {\n+\t{\n+\t\t.virt = 0x00000000,\n+\t\t.phys = 0x00000000,\n+\t\t.size = 0x00000000,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t.virt = 0x40000000,\n+\t\t.phys = 0x40000000,\n+\t\t.size = 0x00000000,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t.virt = 0xa0008000,\n+\t\t.phys = 0xa0008000,\n+\t\t.size = 0x10000,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t.virt = 0xc0000000,\n+\t\t.phys = 0xc0000000,\n+\t\t.size = 0x1f000000,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN |\n+\t\t\t PTE_BLOCK_UXN\n+\t}, {\n+\t\t.virt = 0xfc000000,\n+\t\t.phys = 0xfc000000,\n+\t\t.size = 0x04000000,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_OUTER_SHARE\n+\t}, {\n+\t\t/* List terminator */\n+\t\t0,\n+\t}\n+};\n+\n+struct mm_region *mem_map = gsc_mem_map;\n+\n+static void calculate_available_dram_size(void)\n+{\n+\tphys_size_t total_ddr_size = 0x40000000u;\n+\tphys_size_t non_ecc_region_1_size = 0u;\n+\tphys_size_t non_ecc_region_2_size = 0u;\n+\tu8 index = 0u;\n+\tphys_size_t video_mem_size_a[VIDEOMEM_ARRAY_SIZE] = {\n+\t\t0x0, 0x400000, 0x800000, 0x1000000,\n+\t\t0x2000000, 0x4000000, 0x8000000\n+\t};\n+\n+\ttotal_ddr_size = 1u << (17u - ((readl(DENALI_ROW_DIFF) >> 24u) & 0x7));\n+\ttotal_ddr_size = (total_ddr_size / 8u) * (128u * 1024u);\n+\n+\tif (((readl(DENALI_ECC_ENABLE_DISABLE) >> 16u) & 0x3) > 0u) {\n+\t\ttotal_ddr_size = (total_ddr_size / 8u) * 7u;\n+\n+\t\tif ((readl(DENALI_NON_ECC_REGION_ENABLED) & 0x1) > 0u) {\n+\t\t\tnon_ecc_region_1_size =\n+\t\t\t\t((readl(DENALI_REG_NONECC_REGION_ONE) >> 16u) & 0xfff) -\n+\t\t\t\t(readl(DENALI_REG_NONECC_REGION_ONE) & 0xfff);\n+\t\t\tnon_ecc_region_1_size <<= 20u;\n+\t\t\ttotal_ddr_size -= non_ecc_region_1_size;\n+\t\t}\n+\n+\t\tif ((readl(DENALI_NON_ECC_REGION_ENABLED) & 0x2) > 0u) {\n+\t\t\tnon_ecc_region_2_size =\n+\t\t\t\t((readl(DENALI_REG_NONECC_REGION_TWO) >> 16u) & 0xfff) -\n+\t\t\t\t(readl(DENALI_REG_NONECC_REGION_TWO) & 0xfff);\n+\t\t\tnon_ecc_region_2_size <<= 20u;\n+\t\t\ttotal_ddr_size -= non_ecc_region_2_size;\n+\t\t}\n+\t} else {\n+\t\tindex = readl(VMEMOFF_ADDRESS) & 0x7;\n+\t\tif (index < VIDEOMEM_ARRAY_SIZE)\n+\t\t\ttotal_ddr_size -= video_mem_size_a[index];\n+\t\telse\n+\t\t\ttotal_ddr_size -= DEFAULT_VIDEO_RAM_SIZE;\n+\t\ttotal_ddr_size -= DEFAULT_RESERVED_MEMORY_SIZE;\n+\t}\n+\n+\tgd->ram_size = total_ddr_size;\n+\tgsc_mem_map[0].size = total_ddr_size;\n+\tif ((17u - ((readl(DENALI_ROW_DIFF) >> 24u) & 0x7)) == 16u)\n+\t\tgsc_mem_map[1].size = total_ddr_size;\n+}\n+\n+int dram_init(void)\n+{\n+\tcalculate_available_dram_size();\n+\treturn 0;\n+}\n+\n+static int get_eeprom_mac(uint offset, u8 *v_mac)\n+{\n+\treturn get_eeprom_val(offset, v_mac, 6);\n+}\n+\n+static int set_mac_addr(const char *name, uint offset)\n+{\n+\tint ret;\n+\tu8 v_mac[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};\n+\n+\tret = get_eeprom_mac(offset, v_mac);\n+\tif (ret || !is_valid_ethaddr(v_mac)) {\n+\t\tpr_err(\"Warning: MAC %s - %pM \", name, v_mac);\n+\t\tif (IS_ENABLED(CONFIG_NET_RANDOM_ETHADDR)) {\n+\t\t\tnet_random_ethaddr(v_mac);\n+\t\t\tpr_err(\"invalid, using random MAC - %pM\\n\", v_mac);\n+\t\t} else {\n+\t\t\tpr_err(\"is not valid\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tenv_set(\".flags\", name);\n+\tenv_set(name, NULL);\n+\teth_env_set_enetaddr(name, v_mac);\n+\tdebug(\"%s MAC Address %pM\\n\", name, v_mac);\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\treturn 0;\n+}\n+\n+int misc_init_r(void)\n+{\n+\tset_mac_addr(\"ethaddr\", V_EEPROM_RO_MAC0);\n+\tset_mac_addr(\"eth1addr\", V_EEPROM_RO_MAC1);\n+\treturn 0;\n+}\n+\n+static void arch_timer_start_reg_set(void)\n+{\n+\twritel(ARCH_TIMER_FREQUENCY, ARCH_TIMER_CNTFID0);\n+\twritel(ARCH_TIMER_CNTCR_ENABLE | ARCH_TIMER_CNTCR_HDBG,\n+\t ARCH_TIMER_CNTCR_REG);\n+}\n+\n+int arch_early_init_r(void)\n+{\n+\tif (IS_ENABLED(CONFIG_ARMV8_SPIN_TABLE)) {\n+\t\twritel(gd->relocaddr, SECONDARY_RELEASE_ADDR);\n+\t\tdsb();\n+\t\tasm volatile(\"sev\");\n+\t}\n+\n+\tarch_timer_start_reg_set();\n+\n+\tif (common_phy_poweron_init() == 0)\n+\t\tdebug(\"CommonPhy poweron init succeeded\\n\");\n+\telse\n+\t\tpr_err(\"CommonPhy poweron init failed\\n\");\n+\n+\treturn 0;\n+}\ndiff --git a/board/hpe/gsc/server_id.c b/board/hpe/gsc/server_id.c\nnew file mode 100644\nindex 00000000000..acfcc889f87\n--- /dev/null\n+++ b/board/hpe/gsc/server_id.c\n@@ -0,0 +1,51 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * GSC server_id command\n+ *\n+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.\n+ * Author: Jorge Cisneros <jorge.cisneros@hpe.com>\n+ */\n+\n+#include <env.h>\n+#include <asm/io.h>\n+#include <command.h>\n+\n+#define REGISTER_BASE_ADDRESS\t0xD1000000\n+#define SERVER_ID_OFFSET\t0x0\n+#define SERVER_ID_MASK\t\t0xFFFF00\n+\n+static unsigned int get_server_id(void)\n+{\n+\tunsigned int server_id;\n+\n+\tserver_id = readl(REGISTER_BASE_ADDRESS + SERVER_ID_OFFSET);\n+\tserver_id &= SERVER_ID_MASK;\n+\tserver_id >>= 8;\n+\treturn server_id;\n+}\n+\n+static int do_server_id(struct cmd_tbl *cmdtp, int flag, int argc,\n+\t\t\tchar *const argv[])\n+{\n+\tunsigned int server_id = get_server_id();\n+\tchar env_value[16];\n+\n+\tif (argc == 2) {\n+\t\tif (strcmp(argv[1], \"show\") == 0)\n+\t\t\tprintf(\"Server ID: 0x%04X\\n\", server_id);\n+\t\telse\n+\t\t\tprintf(\"Usage: %s <show>\\n\", cmdtp->name);\n+\t} else {\n+\t\tsnprintf(env_value, sizeof(env_value), \"0x%04x\", server_id);\n+\t\tenv_set(\"server_id\", env_value);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tserver_id, 2, 0, do_server_id,\n+\t\"Get the server ID from the GSC registers\",\n+\t\"<show> - Show the server id instead of setting the environment variable\\n\"\n+\t\" otherwise set an environment variable \\\"server_id\\\" with the value\\n\"\n+);\ndiff --git a/include/configs/gsc.h b/include/configs/gsc.h\nnew file mode 100644\nindex 00000000000..6a199f52674\n--- /dev/null\n+++ b/include/configs/gsc.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * GSC board configuration\n+ *\n+ * (C) Copyright 2019-2025 Hewlett Packard Enterprise Development LP.\n+ */\n+\n+#ifndef _GSC_H_\n+#define _GSC_H_\n+\n+#include <linux/sizes.h>\n+\n+#define CFG_SYS_SDRAM_BASE\t\t0x0\n+#define CFG_SYS_INIT_RAM_ADDR\t\t0x0\n+#define CFG_SYS_INIT_RAM_SIZE\t\t0x100000\n+#define CFG_SYS_INIT_SP_OFFSET \\\n+\t(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)\n+#define CFG_SYS_INIT_SP_ADDR \\\n+\t(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET)\n+\n+#define GICD_BASE\t\t\t0xce000000\n+#define GICR_BASE\t\t\t0xce060000\n+#define SECONDARY_RELEASE_ADDR\t\t0xa0008048\n+\n+#endif\n", "prefixes": [ "7/9" ] }