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GET /api/1.2/patches/2220934/?format=api
{ "id": 2220934, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2220934/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-7-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260408121841.186410-7-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-08T12:18:40", "name": "[v4,6/7] test: dm: add comprehensive tests for NVMEM bit field operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fc849db8d8dda494b2af98a5073103b717db1494", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/1.2/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.2/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-7-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 499133, "url": "http://patchwork.ozlabs.org/api/1.2/series/499133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499133", "date": "2026-04-08T12:18:34", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499133/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220934/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220934/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=CegSHejh;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=h51mvMXV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"CegSHejh\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"h51mvMXV\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frMcL6DThz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 22:21:22 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 06BE783D8A;\n\tWed, 8 Apr 2026 14:21:17 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id BE3088414B; Wed, 8 Apr 2026 14:21:15 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 64E54838BB\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 14:21:13 +0200 (CEST)", "from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63870N7U1620396\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 12:21:12 GMT", "from mail-pg1-f200.google.com (mail-pg1-f200.google.com\n [209.85.215.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddacrjr63-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 12:21:11 +0000 (GMT)", "by mail-pg1-f200.google.com with SMTP id\n 41be03b00d2f7-c6e24ee93a6so565315a12.0\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 05:21:11 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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aswin.murugan@oss.qualcomm.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, ilias.apalodimas@linaro.org,\n mkorpershoek@kernel.org, marek.vasut+renesas@mailbox.org,\n hs@nabladev.com, msp@baylibre.com, ravi@prevas.dk,\n dinesh.maniyam@altera.com, sajattack@postmarketos.org,\n peng.fan@nxp.com, quentin.schulz@cherry.de,\n jamie.gibbons@microchip.com, mateuslima.ti@gmail.com,\n justin@tidylabs.net, wens@kernel.org, n-francis@ti.com,\n ycliang@andestech.com, jerome.forissier@arm.com, clamor95@gmail.com,\n u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v4 6/7] test: dm: add comprehensive tests for NVMEM bit field\n operations", "Date": "Wed, 8 Apr 2026 17:48:40 +0530", "Message-Id": "<20260408121841.186410-7-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "tGiPHm7bZlmSerjcRScg9uuoxbHIDj_u", "X-Proofpoint-GUID": "tGiPHm7bZlmSerjcRScg9uuoxbHIDj_u", "X-Authority-Analysis": "v=2.4 cv=WZs8rUhX c=1 sm=1 tr=0 ts=69d64837 cx=c_pps\n a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=W1BiHNyAc7_2oUjjS0wA:9 a=3WC7DwWrALyhR5TkjVHa:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA4MDExMiBTYWx0ZWRfX+5T7/vg4lAhp\n 6eV7AbJdRKdGdUkkUV1tgdQW0vBGYF+3HAo4DJJLI9Q6MN2UiKPxQnqY34Sh86bLIycVPQLKVd2\n ZbKO3oPmIy2ZkSbNP2vtYbw6SA6eg1yitGoFDgLclHEHf0poDMcWPz8Di2m/g1WCTiVRqpYYaRi\n wBsnuN8d/AKCfWloqSunx0lbOxInZSPxMPVMOaECeRxgM8JjGLtwFdPgce/6DDbffrxL6NitIen\n d1H6A1IwutccUDbkj23H5QLplUBudG65i82soZQKzRwu1eNedd7R+3AthiAxQ8tPsQcM7SXdc10\n x2LEO6S0dX8TZ+OaLpupeLt8cHQtY6H6MLE62Mthr8yqxAF2WL/NjoHzrhcf44RmH5oqtQtqs9i\n z1kmrcCHzesTQjx1mN5CskYZfy49spDcn8elzaDyTjlZLZAztIhi+NzBk0v1dtDOSFWlynWEb1k\n JvX/0YVikQQylVMuTQQ==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 clxscore=1015\n bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080112", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add a mock I2C EEPROM device (nvmem-test@50) to the sandbox device tree\nto support NVMEM bit field operation testing.\n\nAdd test coverage for NVMEM bit field read and write operations to\nvalidate the new bit field support in the NVMEM subsystem.\n\nTest cases include:\n- 1-byte cell with 7-bit field (Qualcomm SDAM reboot reason use case)\n- 4-byte cell with 12-bit field spanning a byte boundary\n- 4-byte cell without a bit field (legacy byte-level access)\n- 4-byte cell with a 16-bit field in the upper 2 bytes\n\nError validation tests cover:\n- Bit field exceeding the cell size\n- Bit field exceeding the 32-bit maximum\n- Invalid bit_offset and nbits combinations\n- Buffer size mismatch in non-bit-field mode\n\nThe tests verify:\n- Correct bit extraction during read operations\n- Read-modify-write behavior preserving unrelated bits\n- Proper error handling for invalid configurations\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\nChanges in v4:\n1. Created separate test file for NVMEM bitfield tests\n2. Fixed test to use correct I2C EEPROM functions\n3. 4-byte cell with 12-bit field spanning byte boundary\n\n---\n arch/sandbox/dts/test.dts | 12 +++\n test/dm/Makefile | 1 +\n test/dm/nvmem.c | 160 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 173 insertions(+)\n create mode 100644 test/dm/nvmem.c", "diff": "diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts\nindex 762c1d9bbe2..4fb4d0a8ef5 100644\n--- a/arch/sandbox/dts/test.dts\n+++ b/arch/sandbox/dts/test.dts\n@@ -959,6 +959,11 @@\n \t\t\t\tsandbox,filename = \"i2c.bin\";\n \t\t\t\tsandbox,size = <256>;\n \t\t\t};\n+\t\t\temul_nvmem_test: emul-nvmem-test {\n+\t\t\t\tcompatible = \"sandbox,i2c-eeprom\";\n+\t\t\t\tsandbox,filename = \"nvmem-test.bin\";\n+\t\t\t\tsandbox,size = <256>;\n+\t\t\t};\n \t\t\temul0: emul0 {\n \t\t\t\tcompatible = \"sandbox,i2c-rtc-emul\";\n \t\t\t};\n@@ -976,6 +981,13 @@\n \t\t\treg = <0x41>;\n \t\t\tsandbox,emul = <&emul_pmic1>;\n \t\t};\n+\n+\t\t/* Mock NVMEM device for bit field testing */\n+\t\tnvmem-test@50 {\n+\t\t\treg = <0x50>;\n+\t\t\tcompatible = \"i2c-eeprom\";\n+\t\t\tsandbox,emul = <&emul_nvmem_test>;\n+\t\t};\n \t};\n \n \ti3c0 {\ndiff --git a/test/dm/Makefile b/test/dm/Makefile\nindex 771b703b737..c60bb077e10 100644\n--- a/test/dm/Makefile\n+++ b/test/dm/Makefile\n@@ -75,6 +75,7 @@ obj-$(CONFIG_CMD_MUX) += mux-cmd.o\n obj-$(CONFIG_MULTIPLEXER) += mux-emul.o\n obj-$(CONFIG_MUX_MMIO) += mux-mmio.o\n obj-y += fdtdec.o\n+obj-$(CONFIG_NVMEM) += nvmem.o\n obj-$(CONFIG_MTD_RAW_NAND) += nand.o\n obj-$(CONFIG_UT_DM) += nop.o\n obj-y += ofnode.o\ndiff --git a/test/dm/nvmem.c b/test/dm/nvmem.c\nnew file mode 100644\nindex 00000000000..dd8d0151d2b\n--- /dev/null\n+++ b/test/dm/nvmem.c\n@@ -0,0 +1,160 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Test for NVMEM bit field support\n+ */\n+\n+#include <dm.h>\n+#include <i2c_eeprom.h>\n+#include <nvmem.h>\n+#include <dm/test.h>\n+#include <test/test.h>\n+#include <test/ut.h>\n+\n+static int nvmem_test_write_raw(struct udevice *dev, uint offset,\n+\t\t\t\tconst void *buf, uint size)\n+{\n+\treturn i2c_eeprom_write(dev, offset, buf, size);\n+}\n+\n+static int nvmem_test_read_raw(struct udevice *dev, uint offset,\n+\t\t\t void *buf, uint size)\n+{\n+\treturn i2c_eeprom_read(dev, offset, buf, size);\n+}\n+\n+/* Test NVMEM bit field operations */\n+static int dm_test_nvmem_bitfield(struct unit_test_state *uts)\n+{\n+\tstruct udevice *nvmem_dev;\n+\tstruct nvmem_cell cell;\n+\tu32 value;\n+\tu8 hw_value_u8;\n+\tu32 hw_value_u32;\n+\n+\tut_assertok(uclass_get_device_by_name(UCLASS_I2C_EEPROM,\n+\t\t\t\t\t \"nvmem-test@50\", &nvmem_dev));\n+\n+\tcell.nvmem = nvmem_dev;\n+\n+\t/* Test reg = <0x0 0x1>; bits = <1 7>: */\n+\tcell.offset = 0x0;\n+\tcell.size = 1;\n+\tcell.bit_offset = 1;\n+\tcell.nbits = 7;\n+\thw_value_u8 = 0x01;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, &hw_value_u8, 1));\n+\tvalue = 0x7f;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0x7f, value);\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, &hw_value_u8, 1));\n+\tut_asserteq(0xff, hw_value_u8);\n+\n+\t/* Test reg = <0x18 0x4>; bits = <4 12>: Spanning byte boundary */\n+\tcell.offset = 0x18;\n+\tcell.size = 4;\n+\tcell.bit_offset = 4;\n+\tcell.nbits = 12;\n+\thw_value_u32 = 0x0000000f;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tvalue = 0xfff;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0xfff, value);\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tut_asserteq(0x0000ffff, hw_value_u32);\n+\n+\t/* Test reg = <0x9 0x4>: Full 4-byte access without bit field */\n+\tcell.offset = 0x9;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 0;\n+\tvalue = 0x12345678;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0x12345678, value);\n+\n+\t/* Test reg = <0xc 0x4>; bits = <16 16>: Upper 2 bytes */\n+\tcell.offset = 0xc;\n+\tcell.bit_offset = 16;\n+\tcell.nbits = 16;\n+\thw_value_u32 = 0x0000ffff;\n+\tut_assertok(nvmem_test_write_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tvalue = 0xffff;\n+\tut_assertok(nvmem_cell_write(&cell, &value, sizeof(value)));\n+\tvalue = 0;\n+\tut_assertok(nvmem_cell_read(&cell, &value, sizeof(value)));\n+\tut_asserteq(0xffff, value);\n+\tut_assertok(nvmem_test_read_raw(nvmem_dev, cell.offset, (u8 *)&hw_value_u32, 4));\n+\tut_asserteq(0xffffffff, hw_value_u32);\n+\n+\treturn 0;\n+}\n+DM_TEST(dm_test_nvmem_bitfield,\n+\tUTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);\n+\n+/* Test NVMEM error handling for invalid configurations */\n+static int dm_test_nvmem_bitfield_errors(struct unit_test_state *uts)\n+{\n+\tstruct udevice *nvmem_dev;\n+\tstruct nvmem_cell cell;\n+\tu32 value;\n+\tint ret;\n+\n+\tut_assertok(uclass_get_device_by_name(UCLASS_I2C_EEPROM,\n+\t\t\t\t\t \"nvmem-test@50\", &nvmem_dev));\n+\n+\t/* Test bit field exceeding cell size */\n+\tcell.nvmem = nvmem_dev;\n+\tcell.offset = 0xd;\n+\tcell.size = 1;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 9;\n+\n+\tvalue = 0xff;\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\tret = nvmem_cell_read(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\t/* Test bit field exceeding 32 bits */\n+\tcell.size = 4;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 33;\n+\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\tret = nvmem_cell_read(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\t/* Test invalid bit_offset + nbits */\n+\tcell.size = 1;\n+\tcell.bit_offset = 7;\n+\tcell.nbits = 2;\n+\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\tret = nvmem_cell_read(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\t/* Test nbits=0 requires buffer size == cell size */\n+\tcell.size = 1;\n+\tcell.bit_offset = 0;\n+\tcell.nbits = 0;\n+\n+\tvalue = 0xff;\n+\tret = nvmem_cell_write(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\tret = nvmem_cell_read(&cell, &value, sizeof(value));\n+\tut_asserteq(-EINVAL, ret);\n+\n+\treturn 0;\n+}\n+DM_TEST(dm_test_nvmem_bitfield_errors,\n+\tUTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);\n", "prefixes": [ "v4", "6/7" ] }