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GET /api/1.2/patches/2220930/?format=api
{ "id": 2220930, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2220930/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-3-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260408121841.186410-3-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-08T12:18:36", "name": "[v4,2/7] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "65dca0dcb0c8123bb245f96ae162b003d1c0dba4", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/1.2/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.2/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260408121841.186410-3-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 499133, "url": "http://patchwork.ozlabs.org/api/1.2/series/499133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499133", "date": "2026-04-08T12:18:34", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499133/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220930/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220930/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=VpzrPtoi;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OjrvMCvd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"VpzrPtoi\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"OjrvMCvd\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frMbc4GdKz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 22:20:44 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 0871684132;\n\tWed, 8 Apr 2026 14:20:42 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id D9525838BB; Wed, 8 Apr 2026 14:20:40 +0200 (CEST)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 7534A84129\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 14:20:38 +0200 (CEST)", "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6388Rc9O1795453\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 12:20:36 GMT", "from mail-pg1-f200.google.com (mail-pg1-f200.google.com\n [209.85.215.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dd51dc3tt-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 12:20:36 +0000 (GMT)", "by mail-pg1-f200.google.com with SMTP id\n 41be03b00d2f7-c741c4cebf3so3912094a12.2\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 05:20:36 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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aswin.murugan@oss.qualcomm.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, sjg@chromium.org, seanga2@gmail.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, ilias.apalodimas@linaro.org,\n mkorpershoek@kernel.org, marek.vasut+renesas@mailbox.org,\n hs@nabladev.com, msp@baylibre.com, ravi@prevas.dk,\n dinesh.maniyam@altera.com, sajattack@postmarketos.org,\n peng.fan@nxp.com, quentin.schulz@cherry.de,\n jamie.gibbons@microchip.com, mateuslima.ti@gmail.com,\n justin@tidylabs.net, wens@kernel.org, n-francis@ti.com,\n ycliang@andestech.com, jerome.forissier@arm.com, clamor95@gmail.com,\n u-boot@lists.denx.de, u-boot-qcom@groups.io", "Subject": "[PATCH v4 2/7] misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver", "Date": "Wed, 8 Apr 2026 17:48:36 +0530", "Message-Id": "<20260408121841.186410-3-aswin.murugan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>", "References": "<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "FfbtbqDL8ACt28sav644pnIB1rNmJgOk", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA4MDExMiBTYWx0ZWRfX5SI5QcMJMvn7\n +iEjyccYXJ9c7fn9f7NralZdwL2zLALI3eFWlKMiH1kaOeZuNKJ8BR+F9jGyKemYhayPd35EbLt\n a1yF95heCzPfUNIXoLDN8S2eExfbKQ7ubwZ6TRUdPsSQidt6t1aEA0F+oNrubpOs/iPpKnYtafn\n Wolpaha5GzkF8B6V58wkSybhPXJgmjI9jYiugOKMqdJdQHOmd2UYalAtWKj8p2g6WUMqeZlK9k5\n hqM2otyMolwztGPdBxYIHk7eGKBjERbu1v3hizgn3fByCvQDn9JTVBj14eP4RNVCEEMoWXhck0n\n rBVkydDdBpw7abkwkhD+KljQcNBjTSZoF2aUAyZt2rStaBiGqfKcgH3F6M8RN1UROdBdw1QDpeL\n PXx+Fka6TsERAc8kafEGPRhuNesOUZ57eVGVlUV8fPN69Hld83tr9MX7lbg+XR41+zzIvWNgZLW\n XqI6vBa+3lvcqklD9GA==", "X-Authority-Analysis": "v=2.4 cv=AcaB2XXG c=1 sm=1 tr=0 ts=69d64814 cx=c_pps\n a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8\n a=xi5d6GjbYgY_MreKiQQA:9 a=3WC7DwWrALyhR5TkjVHa:22", "X-Proofpoint-GUID": "FfbtbqDL8ACt28sav644pnIB1rNmJgOk", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0\n phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080112", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Qualcomm PMICs include SDAM (Shared Direct Access Memory) regions which\nare used to store persistent data like reboot reasons that must survive\nacross reboots.\n\nWithout this driver, U-Boot cannot access PMIC storage, preventing\nreboot-to-bootloader functionality and other features that rely on\npersistent state.\n\nAdd qcom-spmi-sdam driver that:\n- Probes SDAM regions from device tree compatible \"qcom,spmi-sdam\"\n- Implements NVMEM provider interface for standard cell-based access\n- Uses SPMI register read/write operations for data access\n\nThis enables reboot-mode and other subsystems to access PMIC storage\nthrough standard NVMEM APIs.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n---\nChanges in v4:\n1. Use local `fdt_addr_t` variable to prevent silent comparison failure\n on 64-bit platforms\n2. Removed non-standard `qcom,sdam-size` property\n3. Hardcoded SDAM size to 0x100 bytes per hardware specification\n4. Changed `dev_info()` to `dev_dbg()` to reduce boot log verbosity\n\nChanges in v3:\n1. No change in v3\n---\n drivers/misc/Kconfig | 8 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/qcom-spmi-sdam.c | 202 ++++++++++++++++++++++++++++++++++\n 3 files changed, 211 insertions(+)\n create mode 100644 drivers/misc/qcom-spmi-sdam.c", "diff": "diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex a0aa290480e..8ace19c1128 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -92,6 +92,14 @@ config QCOM_GENI\n \t for providing a common interface for various peripherals like UART, I2C, SPI,\n \t etc.\n \n+config QCOM_SPMI_SDAM\n+\tbool \"Qualcomm SPMI SDAM NVMEM driver\"\n+\tdepends on MISC && NVMEM && SPMI\n+\thelp\n+\t Enable support for Qualcomm SPMI SDAM (Shared Direct Access Memory) blocks\n+\t as NVMEM providers. This driver support accessing SDAM blocks in PMICs\n+\t for reboot reason functionality and other NVMEM use cases.\n+\n config ROCKCHIP_EFUSE\n bool \"Rockchip e-fuse support\"\n \tdepends on MISC\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex 1d950f7a0ab..bed2cb63fcb 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -68,6 +68,7 @@ obj-$(CONFIG_QFW_SMBIOS) += qfw_smbios.o\n obj-$(CONFIG_SANDBOX) += qfw_sandbox.o\n endif\n obj-$(CONFIG_QCOM_GENI) += qcom_geni.o\n+obj-$(CONFIG_QCOM_SPMI_SDAM) += qcom-spmi-sdam.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o\ndiff --git a/drivers/misc/qcom-spmi-sdam.c b/drivers/misc/qcom-spmi-sdam.c\nnew file mode 100644\nindex 00000000000..f987c19deb4\n--- /dev/null\n+++ b/drivers/misc/qcom-spmi-sdam.c\n@@ -0,0 +1,202 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Qualcomm SPMI SDAM NVMEM driver\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <dm.h>\n+#include <misc.h>\n+#include <dm/device_compat.h>\n+#include <dm/uclass.h>\n+#include <spmi/spmi.h>\n+\n+#define PID_SHIFT 8\n+#define PID_MASK (0xFF << PID_SHIFT)\n+#define REG_MASK 0xFF\n+#define SDAM_SIZE 0x100\n+\n+struct qcom_sdam_priv {\n+\tu32 base;\n+\tu32 size;\n+\tu32 pmic_usid;\n+\tstruct udevice *spmi_dev;\n+};\n+\n+/**\n+ * qcom_sdam_find_spmi_pmic() - Find SPMI controller and PMIC USID\n+ * @dev: SDAM device\n+ * @spmi_dev: Returns SPMI controller device\n+ * @pmic_usid: Returns PMIC USID for SPMI access\n+ *\n+ * Walks up the device tree to find the PMIC parent and SPMI controller.\n+ * Supports both direct SDAM under PMIC and virtual NVMEM under PON.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_find_spmi_pmic(struct udevice *dev,\n+\t\t\t\t struct udevice **spmi_dev,\n+\t\t\t\t u32 *pmic_usid)\n+{\n+\tstruct udevice *pmic_dev = dev->parent;\n+\tint ret;\n+\n+\tif (!pmic_dev) {\n+\t\tdev_err(dev, \"No parent device found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = dev_read_u32_index(pmic_dev, \"reg\", 0, pmic_usid);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Could not read PMIC USID: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t*spmi_dev = pmic_dev->parent;\n+\tif (!*spmi_dev || (*spmi_dev)->uclass->uc_drv->id != UCLASS_SPMI) {\n+\t\tdev_err(dev, \"Could not find SPMI controller\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev_dbg(dev, \"Found PMIC USID=%d, SPMI controller=%s\\n\",\n+\t\t*pmic_usid, (*spmi_dev)->name);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * qcom_sdam_read() - Read data from SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer to read data into\n+ * @size: Number of bytes to read\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_read().\n+ *\n+ * Return: number of bytes read on success, negative error code on failure\n+ */\n+static int qcom_sdam_read(struct udevice *dev, int offset,\n+\t\t\t void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tu8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_read(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI read failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbuffer[i] = ret;\n+\n+\t\tdev_dbg(dev, \"Read 0x%02x from 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+/**\n+ * qcom_sdam_write() - Write data to SDAM/NVMEM region\n+ * @dev: MISC device (SDAM)\n+ * @offset: Offset within SDAM/NVMEM region\n+ * @buf: Buffer containing data to write\n+ * @size: Number of bytes to write\n+ *\n+ * Uses the same SPMI register access pattern as pmic_qcom.c driver\n+ * for consistency and reliability. This function is called by the\n+ * NVMEM subsystem via misc_write().\n+ *\n+ * Return: number of bytes written on success, negative error code on failure\n+ */\n+static int qcom_sdam_write(struct udevice *dev, int offset,\n+\t\t\t const void *buf, int size)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tconst u8 *buffer = buf;\n+\tint ret;\n+\n+\tif (offset + size > priv->size)\n+\t\treturn -EINVAL;\n+\n+\tfor (size_t i = 0; i < size; i++) {\n+\t\tu32 reg = priv->base + offset + i;\n+\n+\t\tret = spmi_reg_write(priv->spmi_dev, priv->pmic_usid,\n+\t\t\t\t (reg & PID_MASK) >> PID_SHIFT,\n+\t\t\t\t reg & REG_MASK,\n+\t\t\t\t buffer[i]);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(dev, \"SPMI write failed at 0x%x: %d\\n\", reg, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tdev_dbg(dev, \"Wrote 0x%02x to 0x%x (PID=0x%02x REG=0x%02x)\\n\",\n+\t\t\tbuffer[i], reg, (reg & PID_MASK) >> PID_SHIFT, reg & REG_MASK);\n+\t}\n+\n+\treturn size;\n+}\n+\n+static const struct misc_ops qcom_sdam_ops = {\n+\t.read = qcom_sdam_read,\n+\t.write = qcom_sdam_write,\n+};\n+\n+/**\n+ * qcom_sdam_probe() - Probe SDAM device and register as NVMEM provider\n+ * @dev: SDAM device\n+ *\n+ * Handles both real SDAM blocks and virtual NVMEM under PON blocks.\n+ * For virtual NVMEM, adds the parent PON base address to the offset.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_sdam_probe(struct udevice *dev)\n+{\n+\tstruct qcom_sdam_priv *priv = dev_get_priv(dev);\n+\tfdt_addr_t base;\n+\tint ret;\n+\n+\tbase = dev_read_addr(dev);\n+\tif (base == FDT_ADDR_T_NONE) {\n+\t\tdev_err(dev, \"Could not read base address\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->base = base;\n+\tpriv->size = SDAM_SIZE;\n+\n+\tret = qcom_sdam_find_spmi_pmic(dev, &priv->spmi_dev, &priv->pmic_usid);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdev_dbg(dev, \"SDAM base=0x%x size=0x%x PMIC_USID=%d\\n\",\n+\t\tpriv->base, priv->size, priv->pmic_usid);\n+\n+\treturn 0;\n+}\n+\n+static const struct udevice_id qcom_sdam_ids[] = {\n+\t{ .compatible = \"qcom,spmi-sdam\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(qcom_spmi_sdam) = {\n+\t.name = \"qcom-spmi-sdam\",\n+\t.id = UCLASS_MISC,\n+\t.of_match = qcom_sdam_ids,\n+\t.probe = qcom_sdam_probe,\n+\t.ops = &qcom_sdam_ops,\n+\t.priv_auto = sizeof(struct qcom_sdam_priv),\n+};\n", "prefixes": [ "v4", "2/7" ] }