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GET /api/1.2/patches/2213761/?format=api
{ "id": 2213761, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2213761/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/4236113143cc88b45062c1b8a34a1f840f29a0ac.1773991081.git.zhoubinbin@loongson.cn/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/1.2/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<4236113143cc88b45062c1b8a34a1f840f29a0ac.1773991081.git.zhoubinbin@loongson.cn>", "list_archive_url": null, "date": "2026-03-20T07:25:47", "name": "[v6,2/2] i2c: ls2x-v2: Add driver for Loongson-2K0300 I2C controller", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "1f488547cbd536dd73f503ed643ef6a5921cbccd", "submitter": { "id": 84810, "url": "http://patchwork.ozlabs.org/api/1.2/people/84810/?format=api", "name": "Binbin Zhou", "email": "zhoubinbin@loongson.cn" }, "delegate": { "id": 149066, "url": "http://patchwork.ozlabs.org/api/1.2/users/149066/?format=api", "username": "cazzacarna", "first_name": "Andi", "last_name": "Shyti", "email": "andi.shyti@kernel.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/4236113143cc88b45062c1b8a34a1f840f29a0ac.1773991081.git.zhoubinbin@loongson.cn/mbox/", "series": [ { "id": 496770, "url": "http://patchwork.ozlabs.org/api/1.2/series/496770/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/list/?series=496770", "date": "2026-03-20T07:25:46", "name": "i2c: Add Loongson-2K0300 I2C controller support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/496770/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2213761/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2213761/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-i2c+bounces-16598-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-i2c@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-i2c+bounces-16598-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=114.242.206.163", "smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=loongson.cn", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=loongson.cn" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fcYzY02Mzz1y0H\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 20 Mar 2026 18:27:05 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 79CCE301FF81\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 20 Mar 2026 07:26:12 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 97D7035C1AF;\n\tFri, 20 Mar 2026 07:26:11 +0000 (UTC)", "from mail.loongson.cn (mail.loongson.cn [114.242.206.163])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 34D3B35BDBC\n\tfor <linux-i2c@vger.kernel.org>; Fri, 20 Mar 2026 07:26:08 +0000 (UTC)", "from loongson.cn (unknown [223.64.68.17])\n\tby gateway (Coremail) with SMTP id _____8Axz6uP9rxpxPYcAA--.24548S3;\n\tFri, 20 Mar 2026 15:26:07 +0800 (CST)", "from kernelserver (unknown [223.64.68.17])\n\tby front1 (Coremail) with SMTP id qMiowJDxaeCD9rxp7DxZAA--.40268S4;\n\tFri, 20 Mar 2026 15:25:59 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1773991571; cv=none;\n b=Xv3DqMSQ6C/2RO3+BcEbgOJ6BMIXEUQVLiX4OWsTjmqxzo0mT9MMdxL+Jx4SoYQXZC9FfWtsGirbq++vBsH15NwHVCtY5JDXEvuo8qqgLj+bpGTqwFEF7ujZQBaP7zAdwGHkpdTwnPo2nxYMEhQYDoFVbvNQULdl27ohdTV43uw=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1773991571; c=relaxed/simple;\n\tbh=1xrcg5AfRZivLgzDd0oj54uw/3fdjxgO5EG8JbbgqkE=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=Va3orqIOxU1CVNnwwDupch/7PEmpHVld3tM6GkgOq2jy4CBTSrc7JLsRHEynz5cST/za4KhZy/ryzHEyCkyMwTfZwlw6LH4mjxo1/hCxIqlwgQCMudjjpdvn+EM5t5wNUnq7u3mWWAC6ZEpdZH9KrVCRdVCWmekJo0W3qsBP7CQ=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=loongson.cn;\n spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163", "From": "Binbin Zhou <zhoubinbin@loongson.cn>", "To": "Binbin Zhou <zhoubb.aaron@gmail.com>,\n\tHuacai Chen <chenhuacai@loongson.cn>,\n\tAndi Shyti <andi.shyti@kernel.org>,\n\tWolfram Sang <wsa+renesas@sang-engineering.com>,\n\tAndy Shevchenko <andy@kernel.org>,\n\tlinux-i2c@vger.kernel.org", "Cc": "Huacai Chen <chenhuacai@kernel.org>,\n\tXuerui Wang <kernel@xen0n.name>,\n\tloongarch@lists.linux.dev,\n\tBinbin Zhou <zhoubinbin@loongson.cn>", "Subject": "[PATCH v6 2/2] i2c: ls2x-v2: Add driver for Loongson-2K0300 I2C\n controller", "Date": "Fri, 20 Mar 2026 15:25:47 +0800", "Message-ID": "\n <4236113143cc88b45062c1b8a34a1f840f29a0ac.1773991081.git.zhoubinbin@loongson.cn>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<cover.1773991081.git.zhoubinbin@loongson.cn>", "References": "<cover.1773991081.git.zhoubinbin@loongson.cn>", "Precedence": "bulk", "X-Mailing-List": "linux-i2c@vger.kernel.org", "List-Id": "<linux-i2c.vger.kernel.org>", "List-Subscribe": "<mailto:linux-i2c+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-i2c+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxaeCD9rxp7DxZAA--.40268S4", "X-CM-SenderInfo": "p2kr3uplqex0o6or00hjvr0hdfq/1tbiAQEMCGm84cQBQQAAs0", "X-Coremail-Antispam": "1Uk129KBj9fXoWfWw13uFWDuw1DKw1DXr4kKrX_yoW8Zw1xKo\n\tWj93WfXr45Jw18u34jk34Yyr4xXF95CrnrCw4xJrs7Xryjy3WUKFWvkw13Ga4fCryUtr4f\n\tZF95tFWxCFs3t3s8l-sFpf9Il3svdjkaLaAFLSUrUUUU1b8apTn2vfkv8UJUUUU8wcxFpf\n\t9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3\n\tUjIYCTnIWjp_UUUYC7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI\n\t8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG\n\tY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14\n\tv26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF\n\twI0_Gr1j6F4UJwAaw2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2\n\txF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_\n\tJw0_WrylYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x\n\t0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkE\n\tbVWUJVW8JwCFI7km07C267AKxVWUXVWUAwC20s026c02F40E14v26r1j6r18MI8I3I0E74\n\t80Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0\n\tI7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04\n\tk26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7Cj\n\txVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07j2MKZUUUUU=" }, "content": "This I2C module is integrated into the Loongson-2K0300 SoCs.\n\nIt provides multi-master functionality and controls all I2C bus-specific\ntiming, protocols, arbitration, and timing. It supports both standard\nand fast modes.\n\nSigned-off-by: Binbin Zhou <zhoubinbin@loongson.cn>\n---\n MAINTAINERS | 1 +\n drivers/i2c/busses/Kconfig | 10 +\n drivers/i2c/busses/Makefile | 1 +\n drivers/i2c/busses/i2c-ls2x-v2.c | 544 +++++++++++++++++++++++++++++++\n 4 files changed, 556 insertions(+)\n create mode 100644 drivers/i2c/busses/i2c-ls2x-v2.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 96ea84948d76..b6802b3a3101 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -14954,6 +14954,7 @@ M:\tBinbin Zhou <zhoubinbin@loongson.cn>\n L:\tlinux-i2c@vger.kernel.org\n S:\tMaintained\n F:\tDocumentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml\n+F:\tdrivers/i2c/busses/i2c-ls2x-v2.c\n F:\tdrivers/i2c/busses/i2c-ls2x.c\n \n LOONGSON PWM DRIVER\ndiff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig\nindex e11d50750e63..5cad2d0d2569 100644\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -850,6 +850,16 @@ config I2C_LS2X\n \t This driver can also be built as a module. If so, the module\n \t will be called i2c-ls2x.\n \n+config I2C_LS2X_V2\n+\ttristate \"Loongson-2 Fast Speed I2C adapter\"\n+\tdepends on LOONGARCH || COMPILE_TEST\n+\thelp\n+\t If you say yes to this option, support will be included for the\n+\t I2C interface on the Loongson-2K0300 SoCs.\n+\n+\t This driver can also be built as a module. If so, the module\n+\t will be called i2c-ls2x-v2.\n+\n config I2C_MLXBF\n tristate \"Mellanox BlueField I2C controller\"\n depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST\ndiff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile\nindex 547123ab351f..3755c54b3d82 100644\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -80,6 +80,7 @@ obj-$(CONFIG_I2C_KEBA)\t\t+= i2c-keba.o\n obj-$(CONFIG_I2C_KEMPLD)\t+= i2c-kempld.o\n obj-$(CONFIG_I2C_LPC2K)\t\t+= i2c-lpc2k.o\n obj-$(CONFIG_I2C_LS2X)\t\t+= i2c-ls2x.o\n+obj-$(CONFIG_I2C_LS2X_V2)\t+= i2c-ls2x-v2.o\n obj-$(CONFIG_I2C_MESON)\t\t+= i2c-meson.o\n obj-$(CONFIG_I2C_MICROCHIP_CORE)\t+= i2c-microchip-corei2c.o\n obj-$(CONFIG_I2C_MPC)\t\t+= i2c-mpc.o\ndiff --git a/drivers/i2c/busses/i2c-ls2x-v2.c b/drivers/i2c/busses/i2c-ls2x-v2.c\nnew file mode 100644\nindex 000000000000..517760d70169\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-ls2x-v2.c\n@@ -0,0 +1,544 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Loongson-2K0300 I2C controller driver\n+ *\n+ * Copyright (C) 2025-2026 Loongson Technology Corporation Limited\n+ */\n+\n+#include <linux/bitfield.h>\n+#include <linux/bits.h>\n+#include <linux/clk.h>\n+#include <linux/io.h>\n+#include <linux/iopoll.h>\n+#include <linux/i2c.h>\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+#include <linux/regmap.h>\n+#include <linux/time.h>\n+#include <linux/types.h>\n+#include <linux/units.h>\n+\n+/* Loongson-2 fast I2C offset registers */\n+#define LOONGSON2_I2C_CR1\t0x00\t/* I2C control 1 register */\n+#define LOONGSON2_I2C_CR2\t0x04\t/* I2C control 2 register */\n+#define LOONGSON2_I2C_OAR\t0x08\t/* I2C slave address register */\n+#define LOONGSON2_I2C_DR\t0x10\t/* I2C data register */\n+#define LOONGSON2_I2C_SR1\t0x14\t/* I2C status 1 register */\n+#define LOONGSON2_I2C_SR2\t0x18\t/* I2C status 2 register */\n+#define LOONGSON2_I2C_CCR\t0x1c\t/* I2C clock control register */\n+#define LOONGSON2_I2C_TRISE\t0x20\t/* I2C trise register */\n+#define LOONGSON2_I2C_FLTR\t0x24\n+\n+/* Bitfields of I2C control 1 register */\n+#define LOONGSON2_I2C_CR1_PE\t\tBIT(0)\t/* Peripheral enable */\n+#define LOONGSON2_I2C_CR1_START\t\tBIT(8)\t/* Start generation */\n+#define LOONGSON2_I2C_CR1_STOP\t\tBIT(9)\t/* Stop generation */\n+#define LOONGSON2_I2C_CR1_ACK\t\tBIT(10)\t/* Acknowledge enable */\n+#define LOONGSON2_I2C_CR1_POS\t\tBIT(11)\t/* Acknowledge/PEC Position (for data reception) */\n+\n+#define LOONGSON2_I2C_CR1_OP_MASK\t(LOONGSON2_I2C_CR1_START | LOONGSON2_I2C_CR1_STOP)\n+\n+/* Bitfields of I2C control 2 register */\n+#define LOONGSON2_I2C_CR2_FREQ\t\tGENMASK(5, 0)\t/* APB Clock Frequency in MHz */\n+#define LOONGSON2_I2C_CR2_ITERREN\tBIT(8)\t/* Fault-Class Interrupt Enable */\n+#define LOONGSON2_I2C_CR2_ITEVTEN\tBIT(9)\t/* Event-Based Interrupt Enable */\n+#define LOONGSON2_I2C_CR2_ITBUFEN\tBIT(10)\t/* Cache-Class Interrupt Enable */\n+\n+#define LOONGSON2_I2C_CR2_INT_MASK\t\\\n+\t(LOONGSON2_I2C_CR2_ITBUFEN | LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN)\n+\n+/* Bitfields of I2C status 1 register */\n+#define LOONGSON2_I2C_SR1_SB\t\tBIT(0)\t/* Start bit (Master mode) */\n+#define LOONGSON2_I2C_SR1_ADDR\t\tBIT(1)\t/* Address sent (master mode) */\n+#define LOONGSON2_I2C_SR1_BTF\t\tBIT(2)\t/* Byte transfer finished */\n+#define LOONGSON2_I2C_SR1_RXNE\t\tBIT(6)\t/* Data register not empty (receivers) */\n+#define LOONGSON2_I2C_SR1_TXE\t\tBIT(7)\t/* Data register empty (transmitters) */\n+#define LOONGSON2_I2C_SR1_BERR\t\tBIT(8)\t/* Bus error */\n+#define LOONGSON2_I2C_SR1_ARLO\t\tBIT(9)\t/* Arbitration lost (master mode) */\n+#define LOONGSON2_I2C_SR1_AF\t\tBIT(10)\t/* Acknowledge failure */\n+\n+#define LOONGSON2_I2C_SR1_ITEVTEN_MASK\t\\\n+\t(LOONGSON2_I2C_SR1_BTF | LOONGSON2_I2C_SR1_ADDR | LOONGSON2_I2C_SR1_SB)\n+#define LOONGSON2_I2C_SR1_ITBUFEN_MASK\t(LOONGSON2_I2C_SR1_TXE | LOONGSON2_I2C_SR1_RXNE)\n+#define LOONGSON2_I2C_SR1_ITERREN_MASK\t\\\n+\t(LOONGSON2_I2C_SR1_AF | LOONGSON2_I2C_SR1_ARLO | LOONGSON2_I2C_SR1_BERR)\n+\n+/* Bitfields of I2C status 2 register */\n+#define LOONGSON2_I2C_SR2_MSL\t\tBIT(0)\t/* Master/slave */\n+#define LOONGSON2_I2C_SR2_BUSY\t\tBIT(1)\t/* Bus busy */\n+#define LOONGSON2_I2C_SR2_TRA\t\tBIT(2)\t/* Transmitter/receiver */\n+#define LOONGSON2_I2C_SR2_GENCALL\tBIT(4)\t/* General call address (Slave mode) */\n+\n+/* Bitfields of I2C clock control register */\n+#define LOONGSON2_I2C_CCR_CCR\t\tGENMASK(11, 0)\n+#define LOONGSON2_I2C_CCR_DUTY\t\tBIT(14)\n+#define LOONGSON2_I2C_CCR_FS\t\tBIT(15)\n+\n+/* Bitfields of I2C trise register */\n+#define LOONGSON2_I2C_TRISE_SCL\t\tGENMASK(5, 0)\n+\n+#define LOONGSON2_I2C_FREE_SLEEP_US\t10\n+#define LOONGSON2_I2C_FREE_TIMEOUT_US\t(2 * USEC_PER_MSEC)\n+\n+/**\n+ * struct loongson2_i2c_msg - client specific data\n+ * @buf: data buffer\n+ * @count: number of bytes to be transferred\n+ * @result: result of the transfer\n+ * @addr: 8-bit slave addr, including r/w bit\n+ * @stop: last I2C msg to be sent, i.e. STOP to be generated\n+ */\n+struct loongson2_i2c_msg {\n+\tu8\t*buf;\n+\tu32\tcount;\n+\tint\tresult;\n+\tu8 addr;\n+\tbool\tstop;\n+};\n+\n+/**\n+ * struct loongson2_i2c_priv - private data of the controller\n+ * @adapter: I2C adapter for this controller\n+ * @complete: completion of I2C message\n+ * @clk: hw i2c clock\n+ * @regmap: regmap of the I2C device\n+ * @parent_rate_MHz: I2C clock parent rate\n+ * @msg: I2C transfer information\n+ */\n+struct loongson2_i2c_priv {\n+\tstruct i2c_adapter\t\tadapter;\n+\tstruct completion\t\tcomplete;\n+\tstruct clk\t\t\t*clk;\n+\tstruct regmap\t\t\t*regmap;\n+\tunsigned long\t\t\tparent_rate_MHz;\n+\tstruct loongson2_i2c_msg\tmsg;\n+};\n+\n+static void loongson2_i2c_disable_irq(struct loongson2_i2c_priv *priv)\n+{\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_INT_MASK, 0);\n+}\n+\n+static void loongson2_i2c_read_msg(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\tu32 rbuf;\n+\n+\tregmap_read(priv->regmap, LOONGSON2_I2C_DR, &rbuf);\n+\t*msg->buf++ = rbuf;\n+\tmsg->count--;\n+}\n+\n+static void loongson2_i2c_write_msg(struct loongson2_i2c_priv *priv, u8 byte)\n+{\n+\tregmap_write(priv->regmap, LOONGSON2_I2C_DR, byte);\n+}\n+\n+static void loongson2_i2c_terminate_xfer(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\tloongson2_i2c_disable_irq(priv);\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK,\n+\t\t\t msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START);\n+\tcomplete(&priv->complete);\n+}\n+\n+static void loongson2_i2c_handle_write(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\tif (msg->count) {\n+\t\tloongson2_i2c_write_msg(priv, *msg->buf++);\n+\t\tif (!--msg->count)\n+\t\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2,\n+\t\t\t\t\t LOONGSON2_I2C_CR2_ITBUFEN, 0);\n+\t} else {\n+\t\tloongson2_i2c_terminate_xfer(priv);\n+\t}\n+}\n+\n+static void loongson2_i2c_handle_rx_addr(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\tswitch (msg->count) {\n+\tcase 0:\n+\t\tloongson2_i2c_terminate_xfer(priv);\n+\t\tbreak;\n+\tcase 1:\n+\t\t/* Enable NACK and reset POS (Acknowledge position) */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1,\n+\t\t\t\t LOONGSON2_I2C_CR1_ACK | LOONGSON2_I2C_CR1_POS, 0);\n+\t\t/* Set STOP or RepSTART */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK,\n+\t\t\t\t msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START);\n+\t\tbreak;\n+\tcase 2:\n+\t\t/* Enable NACK */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK, 0);\n+\t\t/* Set POS (NACK position) */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_POS,\n+\t\t\t\t LOONGSON2_I2C_CR1_POS);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\t/* Enable ACK */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK,\n+\t\t\t\t LOONGSON2_I2C_CR1_ACK);\n+\t\t/* Reset POS (ACK position) */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_POS, 0);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void loongson2_i2c_isr_error(u32 status, void *data)\n+{\n+\tstruct loongson2_i2c_priv *priv = data;\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\t/* Arbitration lost */\n+\tif (status & LOONGSON2_I2C_SR1_ARLO) {\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_ARLO, 0);\n+\t\tmsg->result = -EAGAIN;\n+\t\tgoto out;\n+\t}\n+\n+\t/*\n+\t * Acknowledge failure:\n+\t * In master transmitter mode a Stop must be generated by software.\n+\t */\n+\tif (status & LOONGSON2_I2C_SR1_AF) {\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_STOP,\n+\t\t\t\t LOONGSON2_I2C_CR1_STOP);\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_AF, 0);\n+\t\tmsg->result = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Bus error */\n+\tif (status & LOONGSON2_I2C_SR1_BERR) {\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_SR1, LOONGSON2_I2C_SR1_BERR, 0);\n+\t\tmsg->result = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\tloongson2_i2c_disable_irq(priv);\n+\tcomplete(&priv->complete);\n+}\n+\n+static void loongson2_i2c_handle_read(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\tswitch (msg->count) {\n+\tcase 1:\n+\t\tloongson2_i2c_disable_irq(priv);\n+\t\tloongson2_i2c_read_msg(priv);\n+\t\tcomplete(&priv->complete);\n+\t\tbreak;\n+\tcase 2:\n+\tcase 3:\n+\t\t/*\n+\t\t * For 2-byte/3-byte reception and for N-byte reception with N > 3, we have to\n+\t\t * wait for byte transferred finished event before reading data.\n+\t\t * Just disable buffer interrupt in order to avoid another system preemption due\n+\t\t * to RX not empty event.\n+\t\t */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_ITBUFEN, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\t/*\n+\t\t * For N byte reception with N > 3 we directly read data register\n+\t\t * until N-2 data.\n+\t\t */\n+\t\tloongson2_i2c_read_msg(priv);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void loongson2_i2c_handle_rx_done(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\n+\tswitch (msg->count) {\n+\tcase 2:\n+\t\t/*\n+\t\t * The STOP/START bit has to be set before reading the last two bytes.\n+\t\t * After that, we could read the last two bytes.\n+\t\t */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_OP_MASK,\n+\t\t\t\t msg->stop ? LOONGSON2_I2C_CR1_STOP : LOONGSON2_I2C_CR1_START);\n+\n+\t\tfor (unsigned int i = msg->count; i > 0; i--)\n+\t\t\tloongson2_i2c_read_msg(priv);\n+\n+\t\tloongson2_i2c_disable_irq(priv);\n+\n+\t\tcomplete(&priv->complete);\n+\t\tbreak;\n+\tcase 3:\n+\t\t/*\n+\t\t * In order to generate the NACK after the last received data byte, enable NACK\n+\t\t * before reading N-2 data.\n+\t\t */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_ACK, 0);\n+\t\tloongson2_i2c_read_msg(priv);\n+\t\tbreak;\n+\tdefault:\n+\t\tloongson2_i2c_read_msg(priv);\n+\t\tbreak;\n+\t}\n+}\n+\n+static irqreturn_t loongson2_i2c_isr_event(int irq, void *data)\n+{\n+\tstruct loongson2_i2c_priv *priv = data;\n+\tstruct device *dev = regmap_get_device(priv->regmap);\n+\tstruct loongson2_i2c_msg *msg = &priv->msg;\n+\tu32 status, ien, event, cr2, possible_status;\n+\n+\tregmap_read(priv->regmap, LOONGSON2_I2C_SR1, &status);\n+\tif (status & LOONGSON2_I2C_SR1_ITERREN_MASK) {\n+\t\tloongson2_i2c_isr_error(status, data);\n+\t\treturn IRQ_NONE;\n+\t}\n+\n+\tregmap_read(priv->regmap, LOONGSON2_I2C_CR2, &cr2);\n+\tien = cr2 & LOONGSON2_I2C_CR2_INT_MASK;\n+\n+\t/* Update possible_status if buffer interrupt is enabled */\n+\tpossible_status = LOONGSON2_I2C_SR1_ITEVTEN_MASK;\n+\tif (ien & LOONGSON2_I2C_CR2_ITBUFEN)\n+\t\tpossible_status |= LOONGSON2_I2C_SR1_ITBUFEN_MASK;\n+\n+\tevent = status & possible_status;\n+\tif (!event) {\n+\t\tdev_dbg(dev, \"spurious evt IRQ (status=0x%08x, ien=0x%08x)\\n\", status, ien);\n+\t\treturn IRQ_NONE;\n+\t}\n+\n+\t/* Start condition generated */\n+\tif (event & LOONGSON2_I2C_SR1_SB)\n+\t\tloongson2_i2c_write_msg(priv, msg->addr);\n+\n+\t/* I2C Address sent */\n+\tif (event & LOONGSON2_I2C_SR1_ADDR) {\n+\t\tif (msg->addr & I2C_M_RD)\n+\t\t\tloongson2_i2c_handle_rx_addr(priv);\n+\t\t/* Clear ADDR flag */\n+\t\tregmap_read(priv->regmap, LOONGSON2_I2C_SR2, &status);\n+\t\t/* Enable buffer interrupts for RX/TX not empty events */\n+\t\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_ITBUFEN,\n+\t\t\t\t LOONGSON2_I2C_CR2_ITBUFEN);\n+\t}\n+\n+\t/* TX empty */\n+\tif ((event & LOONGSON2_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD))\n+\t\tloongson2_i2c_handle_write(priv);\n+\n+\t/* RX not empty */\n+\tif ((event & LOONGSON2_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD))\n+\t\tloongson2_i2c_handle_read(priv);\n+\n+\t/*\n+\t * The BTF (Byte Transfer finished) event occurs when:\n+\t * - in reception: a new byte is received in the shift register\n+\t * but the previous byte has not been read yet from data register\n+\t * - in transmission: a new byte should be sent but the data register\n+\t * has not been written yet\n+\t */\n+\tif (event & LOONGSON2_I2C_SR1_BTF) {\n+\t\tif (msg->addr & I2C_M_RD)\n+\t\t\tloongson2_i2c_handle_rx_done(priv);\n+\t\telse\n+\t\t\tloongson2_i2c_handle_write(priv);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int loongson2_i2c_xfer_msg(struct loongson2_i2c_priv *priv, struct i2c_msg *msg,\n+\t\t\t\t bool is_stop)\n+{\n+\tstruct loongson2_i2c_msg *l_msg = &priv->msg;\n+\tunsigned long timeout;\n+\n+\tl_msg->addr = i2c_8bit_addr_from_msg(msg);\n+\tl_msg->buf = msg->buf;\n+\tl_msg->count = msg->len;\n+\tl_msg->stop = is_stop;\n+\tl_msg->result = 0;\n+\n+\treinit_completion(&priv->complete);\n+\n+\t/* Enable events and errors interrupts */\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2,\n+\t\t\t LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN,\n+\t\t\t LOONGSON2_I2C_CR2_ITEVTEN | LOONGSON2_I2C_CR2_ITERREN);\n+\n+\ttimeout = wait_for_completion_timeout(&priv->complete, priv->adapter.timeout);\n+\tif (!timeout)\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn l_msg->result;\n+}\n+\n+static int loongson2_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num)\n+{\n+\tstruct loongson2_i2c_priv *priv = i2c_get_adapdata(i2c_adap);\n+\tstruct device *dev = regmap_get_device(priv->regmap);\n+\tunsigned int status;\n+\tint ret;\n+\n+\t/* Wait I2C bus free */\n+\tret = regmap_read_poll_timeout(priv->regmap, LOONGSON2_I2C_SR2, status,\n+\t\t\t\t !(status & LOONGSON2_I2C_SR2_BUSY),\n+\t\t\t\t LOONGSON2_I2C_FREE_SLEEP_US,\n+\t\t\t\t LOONGSON2_I2C_FREE_TIMEOUT_US);\n+\tif (ret) {\n+\t\tdev_dbg(dev, \"The I2C bus is busy now.\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Start generation */\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_START,\n+\t\t\t LOONGSON2_I2C_CR1_START);\n+\n+\tfor (unsigned int i = 0; i < num; i++) {\n+\t\tret = loongson2_i2c_xfer_msg(priv, &msgs[i], i == num - 1);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn num;\n+}\n+\n+static u32 loongson2_i2c_func(struct i2c_adapter *adap)\n+{\n+\treturn I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;\n+}\n+\n+static const struct i2c_algorithm loongson2_i2c_algo = {\n+\t.xfer\t\t= loongson2_i2c_xfer,\n+\t.functionality\t= loongson2_i2c_func,\n+};\n+\n+static int loongson2_i2c_adjust_bus_speed(struct loongson2_i2c_priv *priv)\n+{\n+\tstruct device *dev = regmap_get_device(priv->regmap);\n+\tstruct i2c_timings i2c_t;\n+\tu32 val, freq_MHz, ccr;\n+\n+\ti2c_parse_fw_timings(dev, &i2c_t, true);\n+\tpriv->parent_rate_MHz = clk_get_rate(priv->clk);\n+\n+\tif (i2c_t.bus_freq_hz == I2C_MAX_STANDARD_MODE_FREQ) {\n+\t\t /* Select Standard mode */\n+\t\tccr = 0;\n+\t\tval = DIV_ROUND_UP(priv->parent_rate_MHz, i2c_t.bus_freq_hz * 2);\n+\t} else if (i2c_t.bus_freq_hz == I2C_MAX_FAST_MODE_FREQ) {\n+\t\t/* Select Fast mode */\n+\t\tccr = LOONGSON2_I2C_CCR_FS;\n+\t\tval = DIV_ROUND_UP(priv->parent_rate_MHz, i2c_t.bus_freq_hz * 3);\n+\t} else {\n+\t\treturn dev_err_probe(dev, -EINVAL, \"Unsupported speed (%uHz)\\n\", i2c_t.bus_freq_hz);\n+\t}\n+\n+\tFIELD_MODIFY(LOONGSON2_I2C_CCR_CCR, &ccr, val);\n+\tregmap_write(priv->regmap, LOONGSON2_I2C_CCR, ccr);\n+\n+\tfreq_MHz = DIV_ROUND_UP(priv->parent_rate_MHz, HZ_PER_MHZ);\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR2, LOONGSON2_I2C_CR2_FREQ,\n+\t\t\t FIELD_GET(LOONGSON2_I2C_CR2_FREQ, freq_MHz));\n+\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_TRISE, LOONGSON2_I2C_TRISE_SCL,\n+\t\t\t LOONGSON2_I2C_TRISE_SCL);\n+\n+\t/* Enable I2C */\n+\tregmap_update_bits(priv->regmap, LOONGSON2_I2C_CR1, LOONGSON2_I2C_CR1_PE,\n+\t\t\t LOONGSON2_I2C_CR1_PE);\n+\n+\treturn 0;\n+}\n+\n+static const struct regmap_config loongson2_i2c_regmap_config = {\n+\t.reg_bits = 32,\n+\t.val_bits = 32,\n+\t.reg_stride = 4,\n+\t.max_register = LOONGSON2_I2C_TRISE,\n+};\n+\n+static int loongson2_i2c_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct loongson2_i2c_priv *priv;\n+\tstruct i2c_adapter *adap;\n+\tvoid __iomem *base;\n+\tint irq, ret;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tbase = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tpriv->regmap = devm_regmap_init_mmio(dev, base, &loongson2_i2c_regmap_config);\n+\tif (IS_ERR(priv->regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(priv->regmap), \"Failed to init regmap.\\n\");\n+\n+\tpriv->clk = devm_clk_get_enabled(dev, NULL);\n+\tif (IS_ERR(priv->clk))\n+\t\treturn dev_err_probe(dev, PTR_ERR(priv->clk), \"Failed to enable clock.\\n\");\n+\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0)\n+\t\treturn irq;\n+\n+\tadap = &priv->adapter;\n+\tadap->retries = 5;\n+\tadap->nr = pdev->id;\n+\tadap->dev.parent = dev;\n+\tadap->owner = THIS_MODULE;\n+\tadap->algo = &loongson2_i2c_algo;\n+\tadap->timeout = 2 * HZ;\n+\tdevice_set_node(&adap->dev, dev_fwnode(dev));\n+\ti2c_set_adapdata(adap, priv);\n+\tstrscpy(adap->name, pdev->name);\n+\tinit_completion(&priv->complete);\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\tret = loongson2_i2c_adjust_bus_speed(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = devm_request_irq(dev, irq, loongson2_i2c_isr_event, IRQF_SHARED, pdev->name, priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn devm_i2c_add_adapter(dev, adap);\n+}\n+\n+static const struct of_device_id loongson2_i2c_id_table[] = {\n+\t{ .compatible = \"loongson,ls2k0300-i2c\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, loongson2_i2c_id_table);\n+\n+static struct platform_driver loongson2_i2c_driver = {\n+\t.driver = {\n+\t\t.name = \"loongson2-i2c-v2\",\n+\t\t.of_match_table = loongson2_i2c_id_table,\n+\t},\n+\t.probe = loongson2_i2c_probe,\n+};\n+module_platform_driver(loongson2_i2c_driver);\n+\n+MODULE_DESCRIPTION(\"Loongson-2K0300 I2C bus driver\");\n+MODULE_AUTHOR(\"Loongson Technology Corporation Limited\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v6", "2/2" ] }