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    "msgid": "<1509073651-23730-1-git-send-email-shawnguo@kernel.org>",
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    "date": "2017-10-27T03:07:29",
    "name": "[v4,0/2] Add Combo PHY driver for HiSilicon STB SoCs",
    "submitter": {
        "id": 66396,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/66396/?format=api",
        "name": "Shawn Guo",
        "email": "shawnguo@kernel.org"
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            "date": "2017-10-27T03:07:29",
            "name": "Add Combo PHY driver for HiSilicon STB SoCs",
            "version": 4,
            "mbox": "http://patchwork.ozlabs.org/series/10482/mbox/"
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        "From": "Shawn Guo <shawnguo@kernel.org>",
        "To": "Kishon Vijay Abraham I <kishon@ti.com>",
        "Subject": "[PATCH v4 0/2] Add Combo PHY driver for HiSilicon STB SoCs",
        "Date": "Fri, 27 Oct 2017 11:07:29 +0800",
        "Message-Id": "<1509073651-23730-1-git-send-email-shawnguo@kernel.org>",
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        "Cc": "devicetree@vger.kernel.org, Jiancheng Xue <xuejiancheng@hisilicon.com>, \n\tRob Herring <robh+dt@kernel.org>, Jianguo Sun <sunjianguo1@huawei.com>, \n\tShawn Guo <shawn.guo@linaro.org>, linux-arm-kernel@lists.infradead.org",
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        "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org",
        "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org"
    },
    "content": "From: Shawn Guo <shawn.guo@linaro.org>\n\nIt adds device tree bindings and driver support for Combo PHY device\nwhich can be found on HiSilicon STB SoCs.\n\nChanges for v4:\n - Instead of relying on device id, add a new property\n   hisilicon,fixed-mode\n   for combphy device that doesn't support mode select but a fixed phy\n   mode.\n - Move combphy mode select register bits definition to device tree, as\n   it may vary from one device to another.\n\nChanges for v3:\n - Make combphy device be child of peripheral controller and use 'reg'\n   property for mapping combphy configuration registers.\n - Kill \"hisilicon,peripheral-syscon\" property, since parent node is\n   just the syscon controller now.\n - Check combphy id to handle the quirk that combphy0 can not configure\n   mode but always works in USB3 mode.\n - Unify phy .init and .exit hooks for different combphy instances and\n   work modes, as the only quirk we need to handle is that combphy0 can\n   only work in USB3 mode.\n - Better naming for clock and reset, 'ref' to 'ref_clk', 'por' to\n   'por_rst'.\n\nChanges for v2:\n - Move DT bindings into a separate patch.\n - Drop the spurious newline from drivers/phy/Makefile.\n - Use the phy type defines in dt-bindings/phy/phy.h.\n - Use PTR_ERR_OR_ZERO() for checking return from\n   devm_of_phy_provider_register().\n - Add USB3 phy support.\n\nJianguo Sun (2):\n  dt-bindings: add bindings doc for hi3798cv200 combphy\n  phy: add combo phy driver for HiSilicon STB SoCs\n\n .../bindings/phy/phy-hi3798cv200-combphy.txt       |  57 ++++\n drivers/phy/hisilicon/Kconfig                      |   9 +\n drivers/phy/hisilicon/Makefile                     |   1 +\n drivers/phy/hisilicon/phy-histb-combphy.c          | 289 +++++++++++++++++++++\n 4 files changed, 356 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt\n create mode 100644 drivers/phy/hisilicon/phy-histb-combphy.c"
}