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{ "id": 2235082, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2235082/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "list_archive_url": null, "date": "2026-05-08T15:12:00", "name": "[v3,00/32] target/mips: add missing Octeon user-mode support", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com/mbox/", "series": [ { "id": 503407, "url": "http://patchwork.ozlabs.org/api/1.2/series/503407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407", "date": "2026-05-08T15:12:00", "name": "target/mips: add missing Octeon user-mode support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503407/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2235082/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nCWTlp9M;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt1D24zcz1yKd\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 01:13:34 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLMt0-0002bh-FL; Fri, 08 May 2026 11:13:08 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMsv-0002bI-Q6\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:02 -0400", "from mail-oo1-xc36.google.com ([2607:f8b0:4864:20::c36])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMst-0001aU-Pu\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:01 -0400", "by mail-oo1-xc36.google.com with SMTP id\n 006d021491bc7-662efd1bdd4so1203267eaf.0\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 08:12:57 -0700 (PDT)", "from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "X-B4-Tracking": "v=1; b=H4sIAAAAAAAC/32NzQ6CQAwGX4Xs2ZplUf5OvofhgKVAjeySLRIN4\n d1dMF5NeugkX2YWJeSZRJXRojzNLOxsgOQQKexr2xFwE1gZbVJ9MhoGHgUcTuRs+EXYdsBWrMB\n s4ExpkWSZxtagCorRU8uvXX+tvizP251w2pzbomeZnH/v/dlsu18q/p8Kp6HWWRE3bZznWFy6o\n ebHEd2gqnVdP5dnhDPaAAAA", "X-Change-ID": "20260420-mips-octeon-missing-insns-v2-5e693770cf2c", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::c36;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oo1-xc36.google.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series updates MIPS linux-user unaligned-access behavior and fills\nin missing Octeon user-mode instruction support used by existing Octeon\nbinaries.\n\nThe first patches model the Linux/MIPS sysmips ABI pieces needed by\nlinux-user, including MIPS_FLUSH_CACHE, MIPS_ATOMIC_SET, and the\nMIPS_FIXADE policy used to control unaligned scalar access fixups.\nUser-mode unaligned scalar accesses default to software fixups and\nsysmips(MIPS_FIXADE) can toggle SIGBUS/BUS_ADRALN behavior.\n\nThe Octeon patches add integer, indexed memory, atomic, multiplier, COP2\ncrypto, CHORD, and LLM support. The series also adds a small\nmips64/mips64el TCG guest test covering representative Octeon integer,\nmultiplier, and COP2 selector paths. The final patch corrects the\nOcteon68XX CP1 feature bits and FCR defaults.\n\nChanges since v1:\n- Split BADDU/DMUL destination fixes into a preliminary patch.\n- Split the SEQ/SNE decode refactoring into a preliminary patch.\n- Moved Octeon multiplier state to uint64_t arrays and updated VMState.\n- Switched Octeon helper ABIs to i64/uint64_t where applicable.\n- Moved COP2 selector decode/support logic into octeon_translate.c.\n- Added in-tree TCG tests for mips64 and mips64el linux-user.\n- Used switch ranges and g_assert_not_reached() for SHA3/ZUC shared\n selector handling.\n- Dropped Octeon prefixes from generic Camellia helper routines.\n- Replaced the reflected GFM 64-bit carryless multiply loop with\n crypto/clmul.h.\n- Moved the Octeon68XX CP1 CPU-model correction to the end of the\n series.\n- Added migration coverage for Octeon COP2 crypto and LLM sparse state.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges in v3:\n- Rebased on current qemu.git master.\n- Split sysmips support into separate MIPS_FLUSH_CACHE, MIPS_ATOMIC_SET,\n and MIPS_FIXADE patches.\n- Made MIPS_ATOMIC_SET always use the MIPS separate error-result register\n path for successful returns.\n- Removed redundant Octeon MIPS64 checks and target-long guards from the\n translator paths.\n- Removed zero-register fast paths where gen_store_gpr() already handles\n discarded writes.\n- Reworked SEQ/SNE decode and LA* translator helpers as requested.\n- Split the Octeon arithmetic/memory patch into narrower state, indexed\n load, SAA/SAAD, ZCB, multiplier, and test patches.\n- Switched Octeon multiplier limb accumulation to uadd64_overflow().\n- Link to v2: https://lore.kernel.org/qemu-devel/20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com\n\nTo: qemu-devel@nongnu.org\nCc: Laurent Vivier <laurent@vivier.eu>\nCc: Helge Deller <deller@gmx.de>\nCc: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>\nCc: Philippe Mathieu-Daudé <philmd@linaro.org>\nCc: Jiaxun Yang <jiaxun.yang@flygoat.com>\nCc: Aurelien Jarno <aurelien@aurel32.net>\nCc: Aleksandar Rikalo <arikalo@gmail.com>\nCc: Huacai Chen <chenhuacai@kernel.org>\n\n---\nJames Hilliard (32):\n linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE)\n linux-user/mips: implement sysmips(MIPS_ATOMIC_SET)\n linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses\n target/mips: fix Octeon arithmetic destination handling\n target/mips: split Octeon SEQ/SNE decode\n target/mips: drop Octeon zero-register fast paths\n target/mips: add Octeon multiplier state\n target/mips: add Octeon LBX instruction\n target/mips: add Octeon LHUX instruction\n target/mips: add Octeon LWUX instruction\n target/mips: add Octeon SAA instruction\n target/mips: add Octeon SAAD instruction\n target/mips: add Octeon ZCB instruction\n target/mips: add Octeon ZCBT instruction\n target/mips: add Octeon MTM0 instruction\n target/mips: add Octeon MTP0 instruction\n target/mips: add Octeon MTP1 instruction\n target/mips: add Octeon MTP2 instruction\n target/mips: add Octeon MTM1 instruction\n target/mips: add Octeon MTM2 instruction\n target/mips: add Octeon VMULU instruction\n target/mips: add Octeon VMM0 instruction\n target/mips: add Octeon V3MULU instruction\n tests/tcg/mips: add Octeon instruction smoke test\n target/mips: add Octeon LA* atomic instructions\n target/mips: add Octeon COP2 crypto core support\n target/mips: add Octeon SMS4 crypto support\n target/mips: add Octeon SHA3 crypto support\n target/mips: add Octeon ZUC crypto support\n target/mips: add Octeon Camellia crypto support\n target/mips: add Octeon CHORD and LLM COP2 support\n target/mips: expose Octeon68XX floating-point support\n\n MAINTAINERS | 2 +\n linux-user/mips/cpu_loop.c | 5 +\n linux-user/mips/target_syscall.h | 3 +\n linux-user/mips64/target_syscall.h | 3 +\n linux-user/syscall.c | 56 +\n target/mips/cpu-defs.c.inc | 10 +-\n target/mips/cpu.c | 75 +-\n target/mips/cpu.h | 249 +++\n target/mips/helper.h | 6 +\n target/mips/internal.h | 3 +\n target/mips/system/machine.c | 142 ++\n target/mips/tcg/meson.build | 1 +\n target/mips/tcg/octeon.decode | 46 +-\n target/mips/tcg/octeon_crypto.c | 2479 +++++++++++++++++++++++++\n target/mips/tcg/octeon_translate.c | 595 +++++-\n target/mips/tcg/op_helper.c | 100 +\n target/mips/tcg/translate.c | 23 +-\n target/mips/tcg/translate.h | 1 +\n tests/tcg/mips/Makefile.target | 11 +\n tests/tcg/mips/user/isa/octeon/octeon-insns.c | 216 +++\n tests/tcg/mips64/Makefile.target | 20 +\n tests/tcg/mips64el/Makefile.target | 8 +\n 22 files changed, 3997 insertions(+), 57 deletions(-)\n---\nbase-commit: ee7eb612be8f8886d48c1d0c1f1c65e495138f83\nchange-id: 20260420-mips-octeon-missing-insns-v2-5e693770cf2c\n\nBest regards,\n-- \nJames Hilliard <james.hilliard1@gmail.com>" }