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{ "id": 2233983, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2233983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260507062237.78051-1-sibi.sankar@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507062237.78051-1-sibi.sankar@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-05-07T06:22:29", "name": "[RFC,V6,0/8] arm_scmi: vendors: Qualcomm Generic Vendor Extensions", "submitter": { "id": 91759, "url": "http://patchwork.ozlabs.org/api/1.2/people/91759/?format=api", "name": "Sibi Sankar", "email": "sibi.sankar@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260507062237.78051-1-sibi.sankar@oss.qualcomm.com/mbox/", "series": [ { "id": 503109, "url": "http://patchwork.ozlabs.org/api/1.2/series/503109/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=503109", "date": "2026-05-07T06:22:29", "name": "arm_scmi: vendors: Qualcomm Generic Vendor Extensions", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/503109/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2233983/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-14262-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=GAqcjy+U;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=X13NO1uq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14262-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"GAqcjy+U\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"X13NO1uq\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gB2Hk4SNqz1yKd\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 07 May 2026 16:23:14 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id C99B83010D8C\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 7 May 2026 06:22:54 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 905CE334C0D;\n\tThu, 7 May 2026 06:22:54 +0000 (UTC)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 020333254A8\n\tfor <linux-tegra@vger.kernel.org>; Thu, 7 May 2026 06:22:52 +0000 (UTC)", "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6475wTGk1926229\n\tfor <linux-tegra@vger.kernel.org>; Thu, 7 May 2026 06:22:52 GMT", "from mail-pf1-f199.google.com (mail-pf1-f199.google.com\n [209.85.210.199])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e0n2g82qw-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-tegra@vger.kernel.org>; Thu, 07 May 2026 06:22:52 +0000 (GMT)", "by mail-pf1-f199.google.com with SMTP id\n d2e1a72fcca58-83565161a6eso307222b3a.1\n for <linux-tegra@vger.kernel.org>;\n Wed, 06 May 2026 23:22:52 -0700 (PDT)", "from hu-sibis-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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On Qualcomm Glymur and Hamoa SoCs, the memlat governor and the\nmechanism to control the various caches and ram is hosted on the CPU Control\nProcessor (CPUCP) and the method to tweak and start the governor is exposed\nthrough the QCOM SCMI Generic Extension Protocol.\n\nThis series introduces the devfreq scmi client driver that uses the memlat\nalgorithm string hosted on QCOM SCMI Generic Extension Protocol to detect\nmemory latency workloads and control frequency/level of the various memory\nbuses (DDR/LLCC/DDR_QOS). The DDR/LLCC/DDR_QOS are modelled as devfreq\ndevices, with the governor set to remote devfreq governor. This serves as\na way to get a basic insight into the device operation through trans_stat\nand provides for ways to further tweak the parameters of the remote\ngovernor.\n\nTranstat data for DDR/LLCC/DDR_QOS is now available in this series:\n\n#cat llcc/trans_stat \nFrom : To\n315000000 479000000 545000000 725000000 840000000 95900000010900000001211000000 time(ms)\n315000000: 0 3 6 6 6 7 0 30 143956\n479000000: 2 0 7 1 1 1 0 3 356\n545000000: 7 6 0 5 5 0 0 10 1200\n725000000: 3 0 5 0 6 1 0 6 2172\n840000000: 8 2 3 2 0 4 0 12 1188\n959000000: 3 0 1 2 2 0 0 13 272\n1090000000: 0 0 0 0 0 0 0 0 0\n1211000000: 35 4 11 5 11 8 0 0 21684\nTotal transition : 253\n\nQCOM SCMI Generic Vendor protocol background:\nIt was found that a lot of the vendor protocol used internally was\nfor debug/internal development purposes that would either be super\nSoC specific or had to be disabled because of some features being\nfused out during production. This lead to a large number of vendor\nprotocol numbers being quickly consumed and were never released\neither. Using a generic vendor protocol with functionality abstracted\nbehind algorithm strings gave us the flexibility of allowing such\nfunctionality exist during initial development/debugging while\nstill being able to expose functionality like memlat once they have\nmatured enough. The param-ids are certainly expected to act as ABI\nfor algorithms strings like MEMLAT.\n\nThanks in advance for taking time to review the series.\n\nChanges in v5:\n - Combining vendor protocol and the client and moving it\n back into RFC mode.\n - Introduce target_freq attr flag and TRACK_REMOTE devfreq\n governor flag.\n - Add basic remote devfreq governor to give users data like\n transtat [Dmitry]\n - Drop the current design that relies on manual parsing of\n device tree data and move those into SoC specific structs\n - Add Glymur/Mahua/Hamoa/Purwa support in the same series.\n\n Changes in v4:\n - Splitting the series into vendor protocol and memlat client.\n - Also the move the memlat client implementation back to RFC\n due to multiple opens.\n - Use common xfer helper to avoid code duplication [Dmitry]\n - Update enum documentation without duplicate enum info [Dmitry]\n - Update the protol attributes doc with more information. [Cristian]\n\nChanges in v3:\n - Restructure the bindings to mimic IMX [Christian]\n - Add documentation for the qcom generic vendor protocol [Christian/Sudeep]\n - Pick up Rb tag and fixup/re-order elements of the vendor ops [Christian]\n - Follow naming convention and folder structure used by IMX\n - Add missing enum in the vendor protocol and fix documentation [Konrad]\n - Add missing enum in the scmi memlat driver and fix documentation [Konrad]\n - Add checks for max memory and monitor [Shivnandan]\n - Fix typo from START_TIMER -> STOP_TIMER [Shivnandan]\n - Make populate_physical_mask func to void [Shivnandan]\n - Remove unecessary zero set [Shivnandan]\n - Use __free(device node) in init_cpufreq-memfreqmap [Christian/Konrad]\n - Use sdev->dev.of_node directly [Christian]\n - use return dev_err_probe in multiple places [Christian]\n\nChanges in v2:\n - Drop container dvfs memlat container node. [Rob]\n - Move scmi-memlat.yaml to protocol level given that a lot of vendors might end up\n - using the same protocol number. [Rob]\n - Replace qcom,cpulist with the standard \"cpus\" property. [Rob]\n - Fix up compute-type/ipm-ceil required. [Rob]\n - Make driver changes to the accommodate bindings changes. [Rob]\n - Minor fixups in subjects/coverletter.\n - Minor style fixes in dts.\n\nChanges in v1:\n - Add missing bindings for the protocol. [Konrad/Dmitry]\n - Use alternate bindings. [Dmitry/Konrad]\n - Rebase on top of Cristian's \"SCMI multiple vendor protocol support\" series. [Cristian]\n - Add more documentation wherever possible. [Sudeep]\n - Replace pr_err/info with it's dev equivalents.\n - Mixed tabs and initialization cleanups in the memlat driver. [Konrad]\n - Commit message update for the memlat driver. [Dmitry]\n - Cleanups/Fixes suggested for the client driver. [Dmitry/Konrad/Cristian]\n - Use opp-tables instead of memfreq-tbl. [Dmitry/Konrad]\n - Detect physical cpu to deal with variants with reduced cpu count.\n - Add support for DDR_QOS mem_type.\n\nSibi Sankar (8):\n firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation\n firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions\n PM / devfreq: Add new target_freq attribute flag for governors\n PM / devfreq: Add new track_remote flag for governors\n PM / devfreq: Add a governor for tracking remote device frequencies\n PM / devfreq: Introduce the QCOM SCMI Memlat devfreq device\n arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS dvfs\n arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS dvfs\n\n arch/arm64/boot/dts/qcom/glymur.dtsi | 42 ++\n arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 +\n drivers/devfreq/Kconfig | 21 +\n drivers/devfreq/Makefile | 2 +\n drivers/devfreq/devfreq.c | 9 +\n drivers/devfreq/governor_passive.c | 1 +\n drivers/devfreq/governor_performance.c | 1 +\n drivers/devfreq/governor_powersave.c | 1 +\n drivers/devfreq/governor_remote.c | 80 +++\n drivers/devfreq/governor_simpleondemand.c | 1 +\n drivers/devfreq/governor_userspace.c | 1 +\n drivers/devfreq/hisi_uncore_freq.c | 1 +\n drivers/devfreq/scmi-qcom-memlat-cfg.h | 473 ++++++++++++++\n drivers/devfreq/scmi-qcom-memlat-devfreq.c | 582 ++++++++++++++++++\n drivers/devfreq/tegra30-devfreq.c | 3 +-\n drivers/firmware/arm_scmi/Kconfig | 1 +\n drivers/firmware/arm_scmi/Makefile | 1 +\n .../firmware/arm_scmi/vendors/qcom/Kconfig | 15 +\n .../firmware/arm_scmi/vendors/qcom/Makefile | 2 +\n .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 135 ++++\n .../arm_scmi/vendors/qcom/qcom_generic.rst | 211 +++++++\n include/linux/devfreq-governor.h | 4 +\n include/linux/devfreq.h | 1 +\n include/linux/scmi_qcom_protocol.h | 37 ++\n 24 files changed, 1628 insertions(+), 1 deletion(-)\n create mode 100644 drivers/devfreq/governor_remote.c\n create mode 100644 drivers/devfreq/scmi-qcom-memlat-cfg.h\n create mode 100644 drivers/devfreq/scmi-qcom-memlat-devfreq.c\n create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Kconfig\n create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Makefile\n create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c\n create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst\n create mode 100644 include/linux/scmi_qcom_protocol.h\n\n\nbase-commit: 9d0d467c3572e93c5faa2e5906a8bbcd70b24efd" }