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{ "id": 2233968, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2233968/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260507043838.45652-1-npiggin@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260507043838.45652-1-npiggin@gmail.com>", "list_archive_url": null, "date": "2026-05-07T04:38:28", "name": "[v5,0/9] hw/riscv: Add the Tenstorrent Atlantis machine", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/1.2/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260507043838.45652-1-npiggin@gmail.com/mbox/", "series": [ { "id": 503102, "url": "http://patchwork.ozlabs.org/api/1.2/series/503102/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503102", "date": "2026-05-07T04:38:28", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/503102/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2233968/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=DfpgDy+5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62c;\n envelope-from=npiggin@gmail.com; helo=mail-pl1-x62c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introducing Tenstorrent Atlantis!\n\n The Tenstorrent Atlantis platform is a collaboration between Tenstorrent\n and CoreLab Technology. It is based on the Atlantis SoC, which includes\n the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.\n\n The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant\n RISC-V CPU.\n\nI will taking over this series while Joel is away. Many thanks to the\nreviewers on v4, here:\n\nhttps://lore.kernel.org/qemu-devel/20260425131721.932250-1-joel@jms.id.au/T/#mb1ef2824c2f1f37bf4574dc1ef0fb95566c3a2f2\n\nChanges since v4:\n- Drop PCI, to rewok with Designware controller in a later patch.\n- Drop I2C, the model had significant changes so I will work on\n that independently and we can bring that back in Atlantis later.\n- Move the OpenSBI dummy payload hack into tt-atlantis specific code.\n- Remove AIA MAINTAINERS entry since it is already covered.\n- Update microchip_pfsoc to use new discontig boot_info API.\n- Update changelog to explain tt-atlantis machine DTB.\n\nThanks,\nNick\n\nJoel Stanley (3):\n hw/riscv/virt: Move AIA initialisation to helper file\n hw/riscv/aia: Provide number of irq sources\n hw/riscv: Add Tenstorrent Atlantis machine\n\nNicholas Piggin (6):\n hw/riscv/boot: Describe discontiguous memory in boot_info\n hw/riscv/boot: Account for discontiguous memory when loading firmware\n target/riscv: tt-ascalon: Enable Zkr extension\n target/riscv: tt-ascalon: Enable Svadu by removing Svade\n hw/riscv/atlantis: Provide a simple halting payload\n tests/functional/riscv64: Add tt-atlantis tests\n\n MAINTAINERS | 11 +\n docs/system/riscv/tt_atlantis.rst | 32 +\n docs/system/target-riscv.rst | 1 +\n hw/riscv/Kconfig | 10 +\n hw/riscv/aia.c | 93 +++\n hw/riscv/aia.h | 25 +\n hw/riscv/boot.c | 34 +-\n hw/riscv/meson.build | 3 +-\n hw/riscv/microchip_pfsoc.c | 8 +-\n hw/riscv/opentitan.c | 6 +-\n hw/riscv/shakti_c.c | 6 +-\n hw/riscv/sifive_u.c | 6 +-\n hw/riscv/spike.c | 6 +-\n hw/riscv/tt_atlantis.c | 583 +++++++++++++++++++\n hw/riscv/virt-acpi-build.c | 27 +-\n hw/riscv/virt.c | 96 +--\n hw/riscv/xiangshan_kmh.c | 6 +-\n include/hw/riscv/boot.h | 12 +-\n include/hw/riscv/tt_atlantis.h | 51 ++\n include/hw/riscv/virt.h | 2 +-\n roms/seabios-hppa | 2 +-\n target/riscv/cpu.c | 2 +-\n tests/functional/riscv64/meson.build | 1 +\n tests/functional/riscv64/test_opensbi.py | 4 +\n tests/functional/riscv64/test_tt_atlantis.py | 57 ++\n 25 files changed, 975 insertions(+), 109 deletions(-)\n create mode 100644 docs/system/riscv/tt_atlantis.rst\n create mode 100644 hw/riscv/aia.c\n create mode 100644 hw/riscv/aia.h\n create mode 100644 hw/riscv/tt_atlantis.c\n create mode 100644 include/hw/riscv/tt_atlantis.h\n create mode 100755 tests/functional/riscv64/test_tt_atlantis.py" }