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{ "id": 2233144, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2233144/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260505185028.237207-1-dblanzeanu@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>", "list_archive_url": null, "date": "2026-05-05T18:50:21", "name": "[v2,0/7] target/i386/mshv: use hv_vp_register_page for fast register access", "submitter": { "id": 93106, "url": "http://patchwork.ozlabs.org/api/1.2/people/93106/?format=api", "name": "Doru Blânzeanu", "email": "dblanzeanu@linux.microsoft.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260505185028.237207-1-dblanzeanu@linux.microsoft.com/mbox/", "series": [ { "id": 502882, "url": "http://patchwork.ozlabs.org/api/1.2/series/502882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502882", "date": "2026-05-05T18:50:22", "name": "target/i386/mshv: use hv_vp_register_page for fast register access", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502882/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2233144/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=AXMezBjp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g970V0V31z1yJx\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 06 May 2026 04:51:54 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wKKr3-0000fD-FE; Tue, 05 May 2026 14:50:49 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dblanzeanu@linux.microsoft.com>)\n id 1wKKqx-0000eH-Fj\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:44 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <dblanzeanu@linux.microsoft.com>) id 1wKKqt-0006hu-Bw\n for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:42 -0400", "from laptop.localdomain (unknown [86.121.140.248])\n by linux.microsoft.com (Postfix) with ESMTPSA id 4113720B7168;\n Tue, 5 May 2026 11:50:31 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 4113720B7168", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1778007032;\n bh=b37i2jET6adCQZoP/iNN347Vum8ztxt1bYOIGzHMUGM=;\n h=From:To:Cc:Subject:Date:From;\n b=AXMezBjpdS8XW/hK+VN4NBaykNMHDW9bvfGzlr+hiU/5iFEMPSpRtiW/f/MJnDGQR\n gAXLpY9GqjbXJ6ErFf/iuf44Ls8aqmWWo88Qz9XLM9int94cvIX4XXMFUeONSW9TKG\n vumtYiI2a2gi4XOWRsBX2t95K5101yO089/yqtXY=", "From": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Doru_Bl=C3=A2nzeanu?= <dblanzeanu@linux.microsoft.com>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Zhao Liu <zhao1.liu@intel.com>, Wei Liu <wei.liu@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>", "Subject": "[PATCH v2 0/7] target/i386/mshv: use hv_vp_register_page for fast\n register access", "Date": "Tue, 5 May 2026 21:50:21 +0300", "Message-ID": "<20260505185028.237207-1-dblanzeanu@linux.microsoft.com>", "X-Mailer": "git-send-email 2.53.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series adds support for using the hypervisor's vp register page\nin the mshv accelerator to optimize vcpu register access on mmio and pio\nexits.\n\nCurrently, all register reads and write go through hypercalls (ioctls),\nwhich adds overhead on every VM exit. The VP register page is a shared\nmemory page that the hypervisor populates with vcpu register state,\nallowing Qemu to read and write registers directly without hypercalls.\n\nThe series is structured as follows:\n1. Remove the duplicate `fetch_guest_state` function, consolidating\n register loading into `mshv_load_regs`.\n2. Move `mshv_arch_init_vcpu` after vcpu creation so the vcpu fd is\n valid when we need it for mmap.\n3. Define the `hv_vp_register_page` structure in `hvgdk_mini.h`, matching\n the layout used by the Linux kernel's mshv driver.\n4. Set up the register page by mmapping the vcpu fd at init time. If the\n mmap fails, we fall back gracefully to the existing hypercall path.\n5. Use the register page to read registers on VM exit. General purpose\n registers, RIP, RFLAGS, segment registers, and control registers\n (CR0, CR4, CR4, CR8, EFER) are read directly from the page. Registers\n not present on the page (TR, LDTR, GDTR, IDTR, CR2, APIC_BASE) are still\n fetched via hypercall.\n6. Use register page to write registers on vmentry. GP registers,\n RIP, and RFLAGS are written to the page with the appropriate dirty\n bits set, avoiding the hypercall for the standard register store.\n\nThe register page is only used when it has been successfully mmapped and\nthe hypervisor has marked it as valid (`isvalid != 0`). Otherwise, the\nexisting hypercall-based path is used as a fallback.\n\nChanges since v1:\n- move hv_register_page struct definition to hvhdk.h\n- add a compile time guard around regs_page in CPUArchState\n- modify mshv_get_special_regs_vp_page to only retrieve the special\n registers present in the register page (removed TR, LDTR, GDTR, IDTR,\n CR2, APIC_BASE)\n In local testing this hasn't created any regressions, and it is unlikely\n that the mmio operations need this registers.\n We'll want to keep an eye on this in case there are decoded operations\n that rely on fetching these registers on every VM exit.\n- add commit to fix handle_pio_non_str and handle_pio_str to correctly\n store modified registers back to the register page after the pio\n operation, and clear the cpu->accel->dirty flag to avoid the\n mshv_arch_put_registers from resetting some registers state (fpu).\n- modified register page setup to signal an error instead of a warning\n in case mmap fails.\n I am not sure aborting here is fine because it would make some of the\n fallback logic redundant, and I think that's a bigger refactoring.\n\nDoru Blânzeanu (7):\n target/i386/mshv: remove duplicate function for reading vcpu registers\n accel/mshv: move vcpu arch specific initialization after vcpu creation\n include/hw/hyperv: add hv_vp_register_page struct definition\n target/i386/mshv: hv_vp_register_page setup for the vcpu\n target/i386/mshv: use the register page to get registers\n target/i386/mshv: use the register page to set registers\n target/i386/mshv: fix pio handlers clobbering device-modified\n registers\n\n accel/mshv/mshv-all.c | 3 +-\n include/hw/hyperv/hvgdk.h | 2 +\n include/hw/hyperv/hvhdk.h | 105 ++++++++++++++\n target/i386/cpu.h | 5 +\n target/i386/mshv/mshv-cpu.c | 269 ++++++++++++++++++++++++++++--------\n 5 files changed, 327 insertions(+), 57 deletions(-)" }