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{ "id": 2232964, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2232964/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260505105928.38457-1-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.2/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505105928.38457-1-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-05-05T10:59:24", "name": "[0/4] i2c: tegra: Improve DMA mapping, latency, and power management", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/1.2/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260505105928.38457-1-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 502821, "url": "http://patchwork.ozlabs.org/api/1.2/series/502821/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502821", "date": "2026-05-05T10:59:25", "name": "i2c: tegra: Improve DMA mapping, latency, and power management", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502821/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2232964/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-14212-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bFZ5bXaQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Laxman Dewangan <ldewangan@nvidia.com>, Dmitry Osipenko\n\t<digetx@gmail.com>, Andi Shyti <andi.shyti@kernel.org>, Thierry Reding\n\t<thierry.reding@kernel.org>, Jonathan Hunter <jonathanh@nvidia.com>, \"Kartik\n Rajput\" <kkartik@nvidia.com>, Wolfram Sang <wsa@kernel.org>,\n\t<linux-i2c@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "<mochs@nvidia.com>, Akhil R <akhilrajeev@nvidia.com>", "Subject": "[PATCH 0/4] i2c: tegra: Improve DMA mapping, latency,\n and power management", "Date": "Tue, 5 May 2026 16:29:24 +0530", "Message-ID": "<20260505105928.38457-1-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF00021F6F:EE_|DM6PR12MB4250:EE_", "X-MS-Office365-Filtering-Correlation-Id": "978381c7-ea1c-41b3-14ad-08deaa956f93", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|921020|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tj//gSIj2GJ7TQNEEqMvl3Rz5Ou7XxhjW9aLrvwacXzzhMiKWiPT4WnWjyGt8XyZDABbtR13y+LZNfuaeHOM77UMPDYOIcSNtEvS+Zq35ldcDqMXWYjvrVIZlGaDZ0j5ecuh61yOTO3uDa71co1+GGKWV1B/6EPHGaHni6CN5RhBMaE+3BdZ2AWFYe3AoZi0Hx6BQEoAbXJxedSsc1ybEfR1XeJ4A4hRahn5PpTD86QazOl0nbvzU/LGgeWOBnxrlBswxNGs7yRM9zvs1e7rc3ftju61iuFaUz9Qn+5Z+WJlS7Svk73WldFAzT7/21TsvSFcokBgLmEM9abA3KIs2bvVZwGSEgnd3ugicLVnotiOssctG1OC1l7stb5EpD8b60ogHqFAgRLm5Xs1L/kx9X0DD3SL7Y9Hh8nmgr/9BlD+3hUXdxwRvpHlZkBmiZ9VbRHj37MII7s9Jf8c/wx8eI1l/R4uzsMPEbcblRFoHGki//d6JKjXOuGKVgD9R4ZDVqQUUEIELvpEAITsCBnlFXnoBE9zOuaarwruYjWCaf7w+Vg89v6EsUcvgYOxbrqR1yJULezjVrdwyhF8xhPFXp4WRZiSe4F3HxG6Nt03u33tze21m9/I3WOHxZQCksV42udHDkenhkz0pGvSCB++uq8N4vYCT4Osjtaj+AmQATgYdH+q8cI39b/JqhL6Iw1gYSm+jZI7GyRt172PPVU2VFPj6SCSMAt7Fx+97C5wZZgy/pq4oyuPRGHipv8sd9kQOzM5VnD7DwfJP/lpeoQjkTQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(18002099003)(921020)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tS/cHRqpZAS3j2x8YHAsDveelaUsDpVF40JME2fWn6Lyo3nIusLGgVF0noTZX7vgIDX3LNSsX8S0zUgMf3KiejmWY5CmA/hDf2VOLw3/kOgWysN8HvJjEmvUxUiBNZEwr7CIgVC8DSykC151m7Kl5wqKw1YKmpbPCrDCmiMKNpPgq1RLxxAKgX477sQVwz8y9dOB5OpRCJv81eyxq+mVI7ApGj5Hov40w5WLMQCVq4gxWhlzwcH197o7AuMOXVIuopYUxesmOtUXiTEUfylwbZnp++3MaikTnuprk4jt/KhogoQDyqwZ7gUl9rkuYlwkZOuhewpMt+IQ7luG5cd1ZgghYUDYp4PGNUVar3b2qumbqf5Ubexq8A4JeA4LrNMB85T669P+3LLtEhVQc07JUXaZKX7TN0H9eVd8PUjjXaDbaMIzeFXDewmFghtCbG1jV", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 10:59:53.0120\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 978381c7-ea1c-41b3-14ad-08deaa956f93", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF00021F6F.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4250" }, "content": "This series addresses several aspects of the Tegra I2C driver:\n\n- DMA mapping: Use the proper DMA device for buffer allocation to\n ensure correct DMA address translation.\n- Transfer latency: Disable fair arbitration on non-MCTP buses to\n reduce transfer latency.\n- Timing parameters: Update I2C timing values for Tegra410.\n- Power management: Keep the controller available during noirq\n suspend/resume phases for system dependencies.\n\nAkhil R (4):\n i2c: tegra: use dmaengine_get_dma_device() for DMA buffer allocation\n i2c: tegra: Disable fair arbitration for non-MCTP buses\n i2c: tegra: Update Tegra410 I2C timing parameters\n i2c: tegra: Fix NOIRQ suspend/resume\n\n drivers/i2c/busses/i2c-tegra.c | 86 +++++++++++++++++++++++-----------\n 1 file changed, 58 insertions(+), 28 deletions(-)" }