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{ "id": 2231934, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2231934/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260501153553.66382-1-18255117159@163.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260501153553.66382-1-18255117159@163.com>", "list_archive_url": null, "date": "2026-05-01T15:35:51", "name": "[0/2] PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s", "submitter": { "id": 89937, "url": "http://patchwork.ozlabs.org/api/1.2/people/89937/?format=api", "name": "Hans Zhang", "email": "18255117159@163.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260501153553.66382-1-18255117159@163.com/mbox/", "series": [ { "id": 502476, "url": "http://patchwork.ozlabs.org/api/1.2/series/502476/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502476", "date": "2026-05-01T15:35:53", "name": "PCI: cadence: Add 100 ms delay after link up for speeds > 5 GT/s", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502476/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2231934/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-53582-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=ioo1Aime;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53582-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"ioo1Aime\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=117.135.210.5", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6Zsn6jy0z1y04\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 02 May 2026 01:37:17 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 6530C302DF53\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 1 May 2026 15:36:44 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 669EB3D0938;\n\tFri, 1 May 2026 15:36:43 +0000 (UTC)", "from m16.mail.163.com (m16.mail.163.com [117.135.210.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 99F373BFE3F;\n\tFri, 1 May 2026 15:36:39 +0000 (UTC)", "from zhb.. (unknown [])\n\tby gzga-smtp-mtada-g0-3 (Coremail) with SMTP id\n _____wCH4HBbyPRpuOd_Cw--.58479S2;\n\tFri, 01 May 2026 23:35:56 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777649803; cv=none;\n b=qCQgEldYyYN5uZAmyx42cXV4fHLD6ZhWTTs/whpjTeqyxXq1d2ALPJ7NNhoNNg8mnglRqQc4ODdUeEZDX6p7K1vf195aIRUbAltkmUaT1L7xsG2Zj1aNo/CAtYCX3K/L4hUyice83Napq2OCSDY+33wliZPSZ4zPbiSUJhJM/NA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777649803; c=relaxed/simple;\n\tbh=yQK8COgpW/fV6si1NNCHZeFrAK4MGBklWXRBqbL4QVo=;\n\th=From:To:Cc:Subject:Date:Message-Id:MIME-Version;\n b=UAydWP2XH5rtYT6t6oXmUzZ/e2tGh2oXtHRcTOkKBvBAl1TI+Qrbr8vJWBPbV/A1VfohubG0Dx8YWGwPmb5jDFYqe5oJPILzxo/hRT6tr+7fldQNWZ9Z+bRMtvTQVvpZvERaHPOmwHCvTDypKA5sGSz3UJMxdP6qIs6u1aKG9Sw=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=ioo1Aime; arc=none smtp.client-ip=117.135.210.5", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=uR\n\ttlnL49pKeZCApCiJ/CvbaZOCEdzedFqtleNnlK0c0=; b=ioo1AimeJkcaKRj8Fj\n\tIrKD3TGc5GOVSIZgoPTkXi5LkY98r4n09UEesWcztOhKXK7RycZWuiHHtRHuR/VP\n\tIL4tMeVchuWTWHo2rSGcWak9r2li1ZQM+IoaWlpmcKGAm3d6dsSpzQVsd2kfCuXV\n\t23L2nV6FRS82iKj7Vm9l7E/DA=", "From": "Hans Zhang <18255117159@163.com>", "To": "bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tvigneshr@ti.com", "Cc": "robh@kernel.org,\n\ts-vadapalli@ti.com,\n\tlinux-omap@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>", "Subject": "[PATCH 0/2] PCI: cadence: Add 100 ms delay after link up for speeds >\n 5 GT/s", "Date": "Fri, 1 May 2026 23:35:51 +0800", "Message-Id": "<20260501153553.66382-1-18255117159@163.com>", "X-Mailer": "git-send-email 2.34.1", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "_____wCH4HBbyPRpuOd_Cw--.58479S2", "X-Coremail-Antispam": "1Uf129KBjvJXoW7trWfKFW8Zr18uF4kWr48WFg_yoW8Zr18pa\n\ty5Wr4FkFn7Ww4avan7Z3W7Zry5uFn5J3y3Kr4kKa4Iq3sxCr93JF1IqFnaqayagFs5Zr12\n\tyw1qqasrCFsxuFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piGjg7UUUUU=", "X-CM-SenderInfo": "rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBzghGn0yFzAdgAA3D" }, "content": "As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds\ngreater than 5.0 GT/s, software must wait a minimum of 100 ms after Link\ntraining completes before sending a Configuration Request.\n\nThe same requirement has already been addressed for the Synopsys\nDesignWare PCIe controller in commit 80dc18a0cba8d (\"PCI: dwc: Ensure that\ndw_pcie_wait_for_link() waits 100 ms after link up\").\n\nThis series implements the required delay for the Cadence PCIe controller.\n\nPatch 1 introduces a 'max_link_speed' field in struct cdns_pcie and adds\nthe delay logic in cdns_pcie_host_wait_for_link(). Since max_link_speed\ndefaults to 0, the delay is not yet triggered. This patch prepares the\ninfrastructure and references the DWC implementation.\n\nPatch 2 sets the max_link_speed value in the TI J721E glue driver based\non the maximum supported link speed (obtained from the device tree\n\"max-link-speed\" property), thereby activating the delay when the\ncontroller supports speeds greater than 5 GT/s.\n\nOther Cadence-based glue drivers can be updated similarly in follow-up\nwork.\n\n---\nOur company's product is based on the HPA IP from Cadence. When connecting\nto different devices, we encountered issues with the enumeration failure\nwhen connecting to the NVIDIA RTX5070 GPU and the NVMe SSD with PCIe 5.0\ninterface. Our code is based on: 80dc18a0cba8d (\"PCI: dwc: Ensure that\ndw_pcie_wait_for_link() waits 100 ms after link up\").\n---\n\nHans Zhang (2):\n PCI: cadence: Ensure that cdns_pcie_host_wait_for_link() waits 100 ms\n after link up\n PCI: j721e: Set max_link_speed to enable 100 ms delay after link up\n\n drivers/pci/controller/cadence/pci-j721e.c | 1 +\n .../pci/controller/cadence/pcie-cadence-host-common.c | 9 +++++++++\n drivers/pci/controller/cadence/pcie-cadence.h | 2 ++\n 3 files changed, 12 insertions(+)\n\n\nbase-commit: e75a43c7cec459a07d91ed17de4de13ede2b7758" }