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{ "id": 2225487, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2225487/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-21T05:21:45", "name": "[v3,00/14] Add ARM64 support for MSHV accelerator", "submitter": { "id": 92925, "url": "http://patchwork.ozlabs.org/api/1.2/people/92925/?format=api", "name": "Aastha Rawat", "email": "aastharawat@linux.microsoft.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com/mbox/", "series": [ { "id": 500731, "url": "http://patchwork.ozlabs.org/api/1.2/series/500731/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500731", "date": "2026-04-21T05:21:47", "name": "Add ARM64 support for MSHV accelerator", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500731/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2225487/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=IbuY1vym;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n 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linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <aastharawat@linux.microsoft.com>)\n id 1wF3YY-0000cn-Sf; Tue, 21 Apr 2026 01:21:56 -0400", "from localhost (unknown [131.107.147.136])\n by linux.microsoft.com (Postfix) with ESMTPSA id 71DAB20B6F01;\n Mon, 20 Apr 2026 22:21:51 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 71DAB20B6F01", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776748911;\n bh=W96UW654sJD1pJOpxh90zNKS/HrnEn60G7p7PwpBCPw=;\n h=From:Subject:Date:To:Cc:From;\n b=IbuY1vymbO9yrtgtZ0q9h7IqYkgpQ08yf4e+9+3EWUGA7ChzPIxYieRjP0x3HJ/sq\n SuHgDZIQsGHPKSQp6X1zVykA/TQTiXiwUhna7sCUFBo73Lqh99kK0TmyFOCbf7g2Yq\n HeHXdo30wJ1Y42LQ+CHSzYeTCWGSIXWkIBBw0zdE=", "From": "Aastha Rawat <aastharawat@linux.microsoft.com>", "Subject": "[PATCH v3 00/14] Add ARM64 support for MSHV accelerator", "Date": "Tue, 21 Apr 2026 05:21:45 +0000", "Message-Id": "\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAGkJ52kC/4WNQQ6CMBBFr0JmbU0LpIIr72EIactgJxFoptJoC\n He3cgGX7yX//Q0iMmGEa7EBY6JIy5yhOhXgvJkfKGjIDKUstayUElP0qTfO4bM3POm6j2sIAht\n tpWxKg1hD3gbGkd5H995l9hRfC3+Om6R+9l8xKSGFq5RuW3uxTo03MxOvg2d7dssE3b7vX4BSC\n fi+AAAA", "X-Change-ID": "20260311-mshv_accel_arm64_supp-e86b0082aee4", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>, =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Anirudh Rayabharam <anirudh@anirudhrb.com>,\n Aastha Rawat <aastharawat@linux.microsoft.com>,\n Magnus Kulke <magnus.kulke@linux.microsoft.com>, qemu-arm@nongnu.org,\n Alexander Graf <agraf@csgraf.de>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "X-Mailer": "b4 0.15.1", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series adds ARM64 guest support to the MSHV (Microsoft Hypervisor)\naccelerator, enabling QEMU to run aarch64 VMs on Microsoft's hypervisor\nusing the mshv Linux kernel module.\n\nThe first few patches refactor the existing x86 MSHV code to separate\narch-specific pieces from common infrastructure: moving MSR handling to\ntarget/i386, extracting shared register hypercall helpers, provisioning\nhost CPU features, and introducing arch-specific init hooks.\n\nThe remaining patches add the ARM64 backend:\n - vCPU state get/set using hypervisor register hypercalls\n - -cpu host support by querying ID registers from the hypervisor\n - vCPU run loop with MMIO emulation via ESR_EL2 syndrome decoding\n - In-kernel vGICv3 backed by HVCALL_ASSERT_VIRTUAL_INTERRUPT\n - Interrupt control structure adjustments for arm64\n\nWith this series, a standard aarch64 virt machine can be launched with:\n qemu-system-aarch64 -accel mshv -cpu host -M virt ...\n\nCaveats:\n- Live migration is not yet supported.\n\n---\nChanges in v2:\n- Removed PATCH: \"accel/mshv: provision guests with the same features as host\".\n- Extracted common MMIO emulation logic for hvf, whpx and mshv to a\n common place.\n- Fixed checkpatch errors/warnings.\n- Picked up reviewed-by tags.\n- Link to v1: https://lore.kernel.org/qemu-devel/20260311-mshv_accel_arm64_supp-v1-0-c31699b7bc1f@anirudhrb.com\n\n---\nChanges in v3:\n- Handled GPA Intercept in vCPU run loop to fix EDK2 firmware boot.\n- Updated the cover letter: removed caveat about EDK2 firmware boot as\n it is now fixed.\n- Link to v2: https://lore.kernel.org/qemu-devel/20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com/\n\n---\nAastha Rawat (8):\n accel/mshv: move msr.c to target/i386\n accel/mshv: extract common CPU register helpers\n meson, target/arm/mshv: Enable arm64 build & add initial MSHV support\n target/arm/mshv: implement vcpu state operations for ARM64\n target/arm/mshv: implement -cpu host for MSHV\n accel/mshv: Add access_vp_regs synthetic proc features\n target/arm: cpu: Mark MSHV supporting PSCI 1.3\n target/arm: extract MMIO emulation logic for HVF & WHPX\n\nAnirudh Rayabharam (Microsoft) (5):\n accel/mshv: add arch-specific accelerator init hook\n target/arm/mshv: add vCPU run loop\n include/hw/hyperv: adjust hv_interrupt_control structure for arm64\n hw/intc,target/arm/mshv: add MSHV vGICv3 implementation\n MAINTAINERS: updates for MSHV arm64 code\n\nMagnus Kulke (1):\n accel/mshv: implement cpu_thread_is_idle() hook\n\n MAINTAINERS | 8 +\n accel/mshv/irq.c | 2 +\n accel/mshv/meson.build | 4 +-\n accel/mshv/mshv-all.c | 26 +-\n accel/mshv/mshv-cpu-common.c | 151 ++++++++++\n hw/arm/virt.c | 11 +-\n hw/intc/arm_gicv3_common.c | 3 +\n hw/intc/arm_gicv3_mshv.c | 181 ++++++++++++\n hw/intc/meson.build | 1 +\n include/hw/hyperv/hvgdk_mini.h | 130 +++++++++\n include/hw/hyperv/hvhdk.h | 101 ++++++-\n include/hw/hyperv/hvhdk_mini.h | 6 +\n include/hw/intc/arm_gicv3_common.h | 1 +\n include/system/hw_accel.h | 3 +-\n include/system/mshv.h | 2 +\n include/system/mshv_int.h | 5 +\n meson.build | 7 +-\n target/arm/cpu.c | 8 +-\n target/arm/cpu64.c | 24 +-\n target/arm/helper.c | 60 ++++\n target/arm/helper.h | 5 +\n target/arm/hvf/hvf.c | 64 +++--\n target/arm/meson.build | 1 +\n target/arm/mshv/meson.build | 7 +\n target/arm/mshv/mshv-all.c | 567 +++++++++++++++++++++++++++++++++++++\n target/arm/mshv_arm.h | 18 ++\n target/arm/syndrome.h | 37 +++\n target/arm/whpx/whpx-all.c | 62 +---\n target/i386/mshv/meson.build | 2 +\n target/i386/mshv/mshv-all.c | 85 ++++++\n target/i386/mshv/mshv-cpu.c | 170 +----------\n {accel => target/i386}/mshv/msr.c | 0\n 32 files changed, 1480 insertions(+), 272 deletions(-)\n---\nbase-commit: f429c4276c8349f2cc94fb4e46a2a7918bec95c3\nchange-id: 20260311-mshv_accel_arm64_supp-e86b0082aee4\n\nBest regards,\n-- \nAastha Rawat <aastharawat@linux.microsoft.com>" }