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{ "id": 2224626, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2224626/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/cover/20260417173105.1648172-1-peter.maydell@linaro.org/", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/1.2/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-04-17T17:30:48", "name": "[00/17] Handle sub-page granularity in cpu_memory_rw_debug()", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/cover/20260417173105.1648172-1-peter.maydell@linaro.org/mbox/", "series": [ { "id": 500379, "url": "http://patchwork.ozlabs.org/api/1.2/series/500379/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=500379", "date": "2026-04-17T17:30:52", "name": "Handle sub-page granularity in cpu_memory_rw_debug()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500379/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2224626/comments/", "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=lMYbkDNg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fy26w5BhZz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 18 Apr 2026 03:34:00 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-ppc-bounces@nongnu.org>)\n\tid 1wDn2t-00076e-PW; Fri, 17 Apr 2026 13:31:59 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn2A-0006io-U9\n for qemu-ppc@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wDn25-0001xB-WB\n for qemu-ppc@nongnu.org; Fri, 17 Apr 2026 13:31:13 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-43fe62837baso513787f8f.3\n for <qemu-ppc@nongnu.org>; Fri, 17 Apr 2026 10:31:09 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.06\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 17 Apr 2026 10:31:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776447068; x=1777051868; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=4/W82uiyT+afBorDkCWoN1foEc6B52fL1ZLzDNDfnx0=;\n b=lMYbkDNgyc47x32M628ZZVAzTEOa8SJwVuI2HhVwCGi4yFFZvZ+Md7ZaL6dJHb0UkB\n 1gka3l+CpIeQODkJOrfeK14itQGKuKHtEO32CCaW0lC3QuRgjsu0abS/SLm3PEnRniST\n +0uhlk7ua3BOhpKdeSbb3wHrsYL2sJoPRvzK0irZp4ygt+g/25R2ugh6kkfW68Iu5wb0\n xXIhu4rYbrY8XRLuTdhW3GH687S9uXLNPiZ6MoDrsC78WmLo46h9ijST1ORcdHrDrdIW\n 2FtTScp5NEobEly1zOH3RgA4WoD/D53qwyt27cCrt3dwKCO8/aiHGEEZ16f2ublI3Eth\n cxvQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776447068; x=1777051868;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=4/W82uiyT+afBorDkCWoN1foEc6B52fL1ZLzDNDfnx0=;\n b=eUlj2oBxTPoYjTJeMBuGGfIlW9AjrwMyoPCLzTikFgrHZ5Kh/3IXr43Cxu3Wxbmcu0\n eFmabqLcg6b5rBxwBzDsngsV20jtWRpJEXyDx6XM/uF8vlrfmEYEAYy9Gu7qRYs+8R/1\n QMBN8ZruifQlfdZTfkPATF+S0w3oKxeLU6YX/rVG3ZssaSVoJVU6aVasQMAYqNb/h/Ci\n BZcdMJb6mZw6+31RgCrnuy4cBKdVkOtpqWHFf1f3QkSGdQCj2U9diL5e37FHuhbZSCpb\n s84c+vzi2U2NdxqoKH8542mOo3z3oms9nlBBoxVaBfSGMXMlFuiDHl869U+ZQmg0In4B\n yFCQ==", "X-Gm-Message-State": "AOJu0YzYsNvQ3gJhquyW54XLl4I17oA3up40YnJB96ky4WKs2thBq//u\n 1lOrycQeu+4MEU/6kfd6/GsQH/7H6RSFO3EjfqohQTlsAr/fOse4AecTSPhb8YCxWSM=", "X-Gm-Gg": "AeBDievpaYovLHUukEdKTcMDh0mnj+7ikcjKg+iDskO9qX2ukQ9TTvpOtmFVEdUO6+5\n M2x5ZQX8Z8SzPBLhwd5QWebgjevgSg1yd1UFZ0qDeVtzvsYrL5bwlYBMpkPX8GCcvz2WP89+6rk\n HwD2WVQQ1B9O2EFEUyKAefoJyPFVcOHsw8U1/R3OhSLyGglaZZAqmWSEDMiiYL/XR1pZsW+JFGN\n ATyGrmylnVi+szM6az0zxAfZVz/8kLdblYCxarFl8sfxk7zVJTPnJTYsaLXVEY6U8OM/aBKuJ4E\n EDsppie7FSnRtuITFWBQqP7IJ8lR47RBaaZP/WJatyhldkh0gxKptPTjfcOwe2oQqh65zkkTIbC\n Ave76/+8Syag66ilYKMHFMvQ/qQWvvIcpuVAzmhHI27rnj6kPbrhAQXOC9n5OULeqvGiJge5wZe\n 11e3jzV4vlCwRrpTD0CbIFEaGWwPMEHlPkCRVNF0fXJ4pGDhNLgrIo6QKbUxYYU3fPIWZSngtzJ\n s6/Qcxwkm4EYwsJAdZWYvyzjzKkG9rrQtr4lcdM4w==", "X-Received": "by 2002:a05:600c:c085:b0:488:c530:48a0 with SMTP id\n 5b1f17b1804b1-488fb784843mr41389655e9.24.1776447067968;\n Fri, 17 Apr 2026 10:31:07 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n \"Dr. David Alan Gilbert\" <dave@treblig.org>,\n =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>,\n Alexandre Iooss <erdnaxe@crans.org>, Mahmoud Mandour <ma.mandourr@gmail.com>,\n Peter Xu <peterx@redhat.com>, \"Edgar E. Iglesias\" <edgar.iglesias@gmail.com>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>, Nicholas Piggin <npiggin@gmail.com>,\n Chinmay Rath <rathc@linux.ibm.com>, Glenn Miles <milesg@linux.ibm.com>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Ilya Leoshkevich <iii@linux.ibm.com>,\n David Hildenbrand <david@kernel.org>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>", "Subject": "[PATCH 00/17] Handle sub-page granularity in cpu_memory_rw_debug()", "Date": "Fri, 17 Apr 2026 18:30:48 +0100", "Message-ID": "<20260417173105.1648172-1-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::434;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "A while back we added support for targets having memory protection at\na sub-page granularity in TCG: the target returns a CPUTLBEntryFull\nwith a lg_page_size field that tells TCG how big a block of memory the\ntranslation covers. At the moment we only use this in Arm, for the\nM-profile and R-profile MPU which can set protections on small regions\nof memory.\n\nHowever, we forgot about cpu_memory_rw_debug(), which still assumes\nthat translations cover target-page sized regions. It rounds the input\nvirtual address down to a page boundary, translates that, and then\nputs the offset within the page back in again. This causes problems\nfor the Arm MPU case, because if the MPU is set up so that the memory\nat the rounded-down address isn't within a valid region then we\nincorrectly conclude that we can't read the memory at the address we\nwere actually asked about.\nhttps://gitlab.com/qemu-project/qemu/-/work_items/3292 is a report of\nthis for the semihosting case, but it applies also to general debug\naccesses.\n\nThis series fixes this by providing and using a new\ncpu_translate_for_debug() function which takes a non-page-aligned\nvirtual address and returns all of:\n - the exact physical address for that virtual address\n - the memory attributes\n - the lg_page_size the translation is valid for\n\nTo get there, the series starts off by fixing an inconsistency in our\ncurrent get_phys_page_debug and get_phys_page_attrs_debug\nimplementations: most of them can handle non-page-aligned addresses\nand return the corresponding non-page-aligned physical address, but\nsome cannot. As a result most callers need to work around this by\nputting the page-offset bits back into the result. The first seven\npatches fix the targets which weren't accepting and returning\nnon-page-aligned addresses (riscv, alpha, microblaze, sparc, x86,\ns390x, ppc).\n\nAt that point, the \"page\" in the function names is misleading, so we\nrename them to get_phys_addr_debug and get_phys_addr_attrs_debug.\nThen we can remove the workarounds in callsits in the monitor and\nplugins.\n\nOnce all that is complete, we can implement our new\ncpu_translate_for_debug(), either with a new translate_for_debug\nmethod provided by the CPU, or falling back to using\nget_phys_addr_attrs_debug or get_phys_addr_debug for CPUs where\nprotections are still page sized. Finally we can rewrite\ncpu_memory_rw_debug() to use it.\n\nThere is potentially some followup cleanup we could do:\n - the only caller of cpu_get_phys_addr_attrs_debug() now is\n cpu_get_phys_addr_debug() so we could make the latter\n directly call cpu_translate_for_debug()\n - more ambitiously, we could make the 10 callers of\n cpu_get_phys_addr_debug() use cpu_translate_for_debug(),\n so we only have one function for phys-to-virt translations\n instead of three\n - even more ambitious would be to convert the 15 targets\n using get_phys_addr_debug and the two using\n get_phys_addr_attrs_debug to translate_for_debug, so\n we only have one CPU method for phys-to-virt translations\n instead of three\n\nBut I thought this was a good place to stop and get feedback on\nwhether I have the right API for things first, and it does fix the\nreported bug.\n\nthanks\n-- PMM\n\nPeter Maydell (17):\n target/riscv: Make get_phys_page_debug handle non-page-aligned addrs\n target/alpha: Make get_phys_page_debug handle non-page-aligned addrs\n target/microblaze: Make get_phys_page_attrs_debug handle\n non-page-aligned addrs\n target/sparc: Make get_phys_page_debug handle non-page-aligned addrs\n target/x86: Make get_phys_page_attrs_debug handle non-page-aligned\n addrs\n target/s390x: Make get_phys_page_debug handle non-page-aligned addrs\n target/ppc: Make get_phys_page_debug handle non-page-aligned addrs\n target: Rename get_phys_page_debug to get_phys_addr_debug\n target: Rename cpu_get_phys_page_{,attrs_}debug\n hw/core: Update docs for get_phys_addr_{attrs_,}debug\n target/arm: Rename arm_cpu_get_phys_page()\n monitor: hmp_gva2gpa: Don't page-align cpu_get_phys_addr_debug() arg\n and return\n plugins/api.c: Trust cpu_get_phys_addr_debug() return address\n hw/core: Implement new cpu_translate_for_debug()\n hw/core: Implement cpu_get_phys_addr_attrs_debug() with\n cpu_translate_for_debug()\n target/arm: Implement translate_for_debug\n system/physmem: Use translate_for_debug() in cpu_memory_rw_debug()\n\n hw/core/cpu-system.c | 57 +++++++++++++++++++++++---------\n hw/i386/vapic.c | 4 +--\n hw/xtensa/sim.c | 2 +-\n hw/xtensa/xtfpga.c | 2 +-\n include/hw/core/cpu.h | 56 ++++++++++++++++++++++++++-----\n include/hw/core/sysemu-cpu-ops.h | 39 ++++++++++++++++++----\n monitor/hmp-cmds.c | 5 ++-\n plugins/api.c | 4 +--\n system/physmem.c | 38 +++++++++++++--------\n target/alpha/cpu.c | 2 +-\n target/alpha/cpu.h | 2 +-\n target/alpha/helper.c | 3 +-\n target/arm/cpu.c | 2 +-\n target/arm/cpu.h | 3 --\n target/arm/internals.h | 4 +++\n target/arm/ptw.c | 37 ++++++++++++---------\n target/avr/cpu.c | 2 +-\n target/avr/cpu.h | 2 +-\n target/avr/helper.c | 2 +-\n target/hppa/cpu.c | 2 +-\n target/hppa/cpu.h | 2 +-\n target/hppa/mem_helper.c | 2 +-\n target/i386/cpu.c | 2 +-\n target/i386/cpu.h | 2 +-\n target/i386/helper.c | 4 +--\n target/i386/whpx/whpx-all.c | 2 +-\n target/loongarch/cpu-mmu.h | 2 +-\n target/loongarch/cpu.c | 2 +-\n target/loongarch/cpu_helper.c | 2 +-\n target/m68k/cpu.c | 2 +-\n target/m68k/cpu.h | 2 +-\n target/m68k/helper.c | 2 +-\n target/microblaze/cpu.c | 2 +-\n target/microblaze/cpu.h | 2 +-\n target/microblaze/helper.c | 11 +++---\n target/mips/cpu.c | 2 +-\n target/mips/internal.h | 2 +-\n target/mips/system/physaddr.c | 2 +-\n target/or1k/cpu.c | 2 +-\n target/or1k/cpu.h | 2 +-\n target/or1k/mmu.c | 2 +-\n target/ppc/cpu.h | 2 +-\n target/ppc/cpu_init.c | 2 +-\n target/ppc/mmu-hash32.c | 2 +-\n target/ppc/mmu_common.c | 4 +--\n target/riscv/cpu.c | 2 +-\n target/riscv/cpu.h | 2 +-\n target/riscv/cpu_helper.c | 4 +--\n target/rx/cpu.c | 2 +-\n target/rx/cpu.h | 2 +-\n target/rx/helper.c | 2 +-\n target/s390x/cpu-system.c | 2 +-\n target/s390x/helper.c | 20 +++--------\n target/s390x/s390x-internal.h | 1 -\n target/sh4/cpu.c | 2 +-\n target/sh4/cpu.h | 2 +-\n target/sh4/helper.c | 2 +-\n target/sparc/cpu.c | 2 +-\n target/sparc/cpu.h | 2 +-\n target/sparc/mmu_helper.c | 10 +++---\n target/tricore/cpu.c | 2 +-\n target/tricore/cpu.h | 2 +-\n target/tricore/helper.c | 2 +-\n target/xtensa/cpu.c | 2 +-\n target/xtensa/cpu.h | 2 +-\n target/xtensa/mmu_helper.c | 2 +-\n target/xtensa/xtensa-semi.c | 2 +-\n 67 files changed, 250 insertions(+), 152 deletions(-)" }