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{ "id": 2224376, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2224376/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417105618.3621-1-magnuskulke@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-17T10:55:44", "name": "[00/34] Add migration support to the MSHV accelerator", "submitter": { "id": 90753, "url": "http://patchwork.ozlabs.org/api/1.2/people/90753/?format=api", "name": "Magnus Kulke", "email": "magnuskulke@linux.microsoft.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417105618.3621-1-magnuskulke@linux.microsoft.com/mbox/", "series": [ { "id": 500310, "url": "http://patchwork.ozlabs.org/api/1.2/series/500310/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310", "date": "2026-04-17T10:55:44", "name": "Add migration support to the MSHV accelerator", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500310/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2224376/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=oUI+I66V;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsKB1J58z1yHp\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:57:16 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgsB-0000Iy-Hd; Fri, 17 Apr 2026 06:56:31 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <magnuskulke@linux.microsoft.com>)\n id 1wDgs9-0000Ih-IC\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:29 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <magnuskulke@linux.microsoft.com>) id 1wDgs7-0001HQ-AN\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:56:29 -0400", "from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 5E8B420B7128;\n Fri, 17 Apr 2026 03:56:21 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 5E8B420B7128", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423384;\n bh=kT+fZO67+FFVyM48Jt/bh2LO+EU7++uA6l5Zv1+8NLc=;\n h=From:To:Cc:Subject:Date:From;\n b=oUI+I66VJt/nBuWkAhLvnvbtE88rVDiUdYrh3K82v7liYYOMt3JxMjKpKGcTNR6iG\n 7T5HP4NcvmBnTPuxJW4rns1hUqTGF0S4teD3mJ6YijwXOQKBLKNVm4/7Mpe+0cYjea\n tAqu2Wp6s+aJzJGHBMOYf4v823CuRczNw8Lp9AXc=", "From": "Magnus Kulke <magnuskulke@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "kvm@vger.kernel.org, Magnus Kulke <magnuskulke@microsoft.com>,\n Wei Liu <liuwe@microsoft.com>, \"Michael S. Tsirkin\" <mst@redhat.com>,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Zhao Liu <zhao1.liu@intel.com>,\n Richard Henderson <richard.henderson@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Alex Williamson <alex@shazbot.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Marcelo Tosatti <mtosatti@redhat.com>", "Subject": "[PATCH 00/34] Add migration support to the MSHV accelerator", "Date": "Fri, 17 Apr 2026 12:55:44 +0200", "Message-Id": "<20260417105618.3621-1-magnuskulke@linux.microsoft.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hey all, This is a patch series for live migration support in the MSHV\naccelerator. Since this is somewhat invasive and touches various parts\noutside of the accel's folder hierarchies I'm sending an RFC series to\ncollect early feedback.\n\nThis patches are sent in sent in isolation, but for LM to be fully\nfunctional we will require require the recently submitted patch series\n\"Support QEMU cpu models in MSHV accelerator\" (at v6 currently) to be\nmerged, since on some hosts we will need the CPUID infra to disable\nfeatures that we currently are not able to migrate yet (e.g. AMX tiles).\n\nIn this series we perform some preperatory refactorings and introduce\nnew abstractions where required, particulary for irqchips and MSR\nlogic. We also have to introduce some generic logic for XSAVE\nde/compaction to allow migration of XSAVE state.\n\nNote: there is some pending optimization to avoid a buffer copy\nand rework existing xsave helper code to be generic over a\ncompacted or standard layout. We'll address this in a later revision\nor in a discrete patch.\n\nThe guest state components that are covered by migration are:\n\n- standard regs\n- special regs\n- xcr0\n- (legacy) FPU regs\n- XSAVE\n- LAPIC\n- MSRs\n- SynIC state (SIMP, SIEFP, STIMER)\n- pending interrupts/exceptions\n- MP state (AP cpu modes)\n\nFinally, routines for dirty-page tracking to reduce migration downtime\nhave beend added and integrated in the respective hooks.\n\nbest,\n\nmagnus\n\nChanges since RFC:\n\n- Added CET SS/IBT MSR migration\n- Assert 64bit padding on CPUX86State->sysenter_cs statically\n\nMagnus Kulke (34):\n target/i386/mshv: use arch_load/store_reg fns\n target/i386/mshv: use generic FPU/xcr0 state\n target/i386/mshv: impl init/load/store_vcpu_state\n accel/accel-irq: add AccelRouteChange abstraction\n accel/accel-irq: add generic begin_route_changes\n accel/accel-irq: add generic commit_route_changes\n accel/mshv: add irq_routes to state\n accel/mshv: update s->irq_routes in add_msi_route\n accel/mshv: update s->irq_routes in update_msi_route\n accel/mshv: update s->irq_routes in release_virq\n accel/mshv: use s->irq_routes in commit_routes\n accel/mshv: reserve ioapic routes on s->irq_routes\n accel/mshv: remove redundant msi controller\n target/i386/mshv: move apic logic into own file\n target/i386/mshv: remove redundant apic helpers\n target/i386/mshv: migrate LAPIC state\n target/i386/mshv: move msr code to arch\n accel/mshv: store partition proc features\n target/i386/mshv: expose msvh_get_generic_regs\n target/i386/mshv: migrate MSRs\n target/i386/mshv: migrate MTRR MSRs\n target/i386/mshv: migrate Synic SINT MSRs\n target/i386/mshv: migrate CET/SS MSRs\n target/i386/mshv: migrate SIMP and SIEFP state\n target/i386/mshv: migrate STIMER state\n accel/mshv: introduce SaveVMHandler\n accel/mshv: write synthetic MSRs after migration\n accel/mshv: migrate REFERENCE_TIME\n target/i386/mshv: migrate pending ints/excs\n target/i386: add de/compaction to xsave_helper\n target/i386/mshv: migrate XSAVE state\n target/i386/mshv: reconstruct hflags after load\n target/i386/mshv: migrate MP_STATE\n accel/mshv: enable dirty page tracking\n\n accel/accel-irq.c | 41 +-\n accel/kvm/kvm-all.c | 6 +-\n accel/mshv/irq.c | 360 ++++++------\n accel/mshv/mem.c | 211 +++++++\n accel/mshv/meson.build | 1 -\n accel/mshv/mshv-all.c | 243 +++++++-\n accel/mshv/msr.c | 375 -------------\n accel/stubs/kvm-stub.c | 2 +-\n accel/stubs/mshv-stub.c | 6 +-\n hw/intc/apic_common.c | 3 +\n hw/misc/ivshmem-pci.c | 8 +-\n hw/vfio/pci.c | 11 +-\n hw/virtio/virtio-pci.c | 3 +-\n include/accel/accel-route.h | 17 +\n include/hw/hyperv/hvgdk_mini.h | 33 ++\n include/hw/hyperv/hvhdk.h | 150 +++++\n include/hw/i386/apic_internal.h | 5 +\n include/system/accel-irq.h | 6 +-\n include/system/kvm.h | 23 +-\n include/system/mshv.h | 15 +-\n include/system/mshv_int.h | 89 +--\n target/i386/cpu.h | 14 +-\n target/i386/kvm/kvm.c | 5 +-\n target/i386/machine.c | 46 ++\n target/i386/mshv/meson.build | 3 +\n target/i386/mshv/mshv-apic.c | 78 +++\n target/i386/mshv/mshv-cpu.c | 958 +++++++++++++++++++++++---------\n target/i386/mshv/msr.c | 467 ++++++++++++++++\n target/i386/mshv/synic.c | 206 +++++++\n target/i386/xsave_helper.c | 255 +++++++++\n 30 files changed, 2684 insertions(+), 956 deletions(-)\n delete mode 100644 accel/mshv/msr.c\n create mode 100644 include/accel/accel-route.h\n create mode 100644 target/i386/mshv/mshv-apic.c\n create mode 100644 target/i386/mshv/msr.c\n create mode 100644 target/i386/mshv/synic.c" }