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{ "id": 2224358, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2224358/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417104652.17857-1-xiaoou@iscas.ac.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "list_archive_url": null, "date": "2026-04-17T10:46:37", "name": "[00/14] target/riscv: add support for RISC-V P extension (v0.20 draft)", "submitter": { "id": 89843, "url": "http://patchwork.ozlabs.org/api/1.2/people/89843/?format=api", "name": "Molly Chen", "email": "xiaoou@iscas.ac.cn" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417104652.17857-1-xiaoou@iscas.ac.cn/mbox/", "series": [ { "id": 500307, "url": "http://patchwork.ozlabs.org/api/1.2/series/500307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500307", "date": "2026-04-17T10:46:37", "name": "target/riscv: add support for RISC-V P extension (v0.20 draft)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500307/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2224358/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxs6K4yj7z1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Apr 2026 20:47:53 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wDgjE-00011M-R7; Fri, 17 Apr 2026 06:47:16 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgjA-000104-PK; Fri, 17 Apr 2026 06:47:12 -0400", "from smtp21.cstnet.cn ([159.226.251.21] helo=cstnet.cn)\n by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256)\n (Exim 4.90_1) (envelope-from <xiaoou@iscas.ac.cn>)\n id 1wDgj7-0007tO-Gz; Fri, 17 Apr 2026 06:47:12 -0400", "from Huawei.localdomain (unknown [36.110.52.2])\n by APP-01 (Coremail) with SMTP id qwCowAB3H2ulD+JpLDmSDQ--.804S2;\n Fri, 17 Apr 2026 18:47:02 +0800 (CST)" ], "From": "Molly Chen <xiaoou@iscas.ac.cn>", "To": "palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com,\n daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,\n chao.liu.zevorn@gmail.com", "Cc": "xiaoou@iscas.ac.cn,\n\tqemu-riscv@nongnu.org,\n\tqemu-devel@nongnu.org", "Subject": "[PATCH 00/14] target/riscv: add support for RISC-V P extension (v0.20\n draft)", "Date": "Fri, 17 Apr 2026 18:46:37 +0800", "Message-Id": "<20260417104652.17857-1-xiaoou@iscas.ac.cn>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qwCowAB3H2ulD+JpLDmSDQ--.804S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxCr13KF4fWw1DXr1DWF1DGFg_yoW5Xryfpr\n s5G34aka1DJ3yxWw1ftr4DCry5WF4rWr4rAan7Jw18tan8tFWFyr9Fgw1akFy5JFy8Wr12\n 93Wj9r13Zr4UAF7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUkl14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j\n 6F4UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s\n 0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII\n jxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr\n 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v26r4a\n 6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI\n 0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y\n 0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxV\n W8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1l\n IxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sREtCztUUUU\n U==", "X-Originating-IP": "[36.110.52.2]", "X-CM-SenderInfo": "50ld003x6l2u1dvotugofq/", "Received-SPF": "pass client-ip=159.226.251.21; envelope-from=xiaoou@iscas.ac.cn;\n helo=cstnet.cn", "X-Spam_score_int": "-21", "X-Spam_score": "-2.2", "X-Spam_bar": "--", "X-Spam_report": "(-2.2 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.998,\n HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series adds support for the RISC-V Packed SIMD (P) extension.\n\nThe P extension defines packed-SIMD fixed-point operations intended\nfor DSP-style workloads such as multimedia and signal processing.\nThese instructions operate on packed subword elements within\ngeneral-purpose registers (GPRs).\n\nThe implementation follows the current development draft of the\nspecification (v0.20):\n\n https://www.jhauser.us/RISCV/ext-P/\n\nAll instructions defined prior to the v0.20 update were verified\nusing a simple instruction coverage test suite:\n\n https://github.com/mollybuild/qemu-riscv-test-uart\n\nInstructions newly introduced in v0.20 were not tested yet because\ntoolchain support for generating them is still under development.\n\nThe implementation focuses on functional correctness and ISA coverage.\nPerformance optimizations were not considered at this stage.\n\nFeedback on implementation details would be highly appreciated.\n\nCo-Authored by: Yin Zhang <zhangyin2018@iscas.ac.cn>\nCo-Authored by: Dajun Huang <djhuang_1@std.uestc.edu.cn>\nCo-Authored by: Zhiyuan Yang <zhiyuan.plct@isrc.iscas.ac.cn> \n\nMolly Chen (14):\n target/riscv: rvp: Add option defines and dependency check for packed\n simd extension\n target/riscv: rvp: add arithmetic instructions,including saturating\n and non-saturating operations\n target/riscv: rvp: add averaging operations\n target/riscv: rvp: add absolute value and difference,comparison and\n mask generation operations\n target/riscv: rvp: add shift operations\n target/riscv: rvp: add exchange operations\n target/riscv: rvp: add horizontal reduction, pack, merge and cout\n leading operations\n target/riscv: rvp: add pure multiplication operations\n target/riscv: rvp: add multiply-accumulate operations\n target/riscv: rvp: add Q-format multiplication operations\n target/riscv: rvp: add two-way and four-way multiply and accumulate\n operations\n target/riscv: rvp: add load and replicate instructions.\n target/riscv: rvp: add rv32-only register-pair instructions\n target/riscv: rvp: update to v020, add SHL and PNCLIP[U]P.*\n instructions\n\n target/riscv/cpu.c | 5 +-\n target/riscv/cpu.h | 1 +\n target/riscv/helper.h | 531 ++\n target/riscv/insn32.decode | 829 ++\n target/riscv/insn_trans/trans_rvp.c.inc | 1691 ++++\n target/riscv/meson.build | 3 +-\n target/riscv/psimd_helper.c | 9452 +++++++++++++++++++++++\n target/riscv/tcg/tcg-cpu.c | 16 +\n target/riscv/translate.c | 3 +\n 9 files changed, 12528 insertions(+), 3 deletions(-)\n create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc\n create mode 100644 target/riscv/psimd_helper.c" }