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{ "id": 2223435, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2223435/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260415105552.622421-1-skolothumtho@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "list_archive_url": null, "date": "2026-04-15T10:55:21", "name": "[v4,00/31] hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.2/people/91580/?format=api", "name": "Shameer Kolothum Thodi", "email": "skolothumtho@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260415105552.622421-1-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 499965, "url": "http://patchwork.ozlabs.org/api/1.2/series/499965/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499965", "date": "2026-04-15T10:55:21", "name": "hw/arm/virt: Introduce Tegra241 CMDQV support for accelerated SMMUv3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499965/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2223435/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=E1Mih2iH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c007::2;\n envelope-from=skolothumtho@nvidia.com;\n helo=MW6PR02CU001.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>, <clg@redhat.com>,\n <alex@shazbot.org>, <nicolinc@nvidia.com>, <nathanc@nvidia.com>,\n <mochs@nvidia.com>, <jan@nvidia.com>, <jgg@nvidia.com>,\n <jonathan.cameron@huawei.com>, <zhenzhong.duan@intel.com>,\n <kjaju@nvidia.com>, <phrdina@redhat.com>, <skolothumtho@nvidia.com>", "Subject": "[PATCH v4 00/31] hw/arm/virt: Introduce Tegra241 CMDQV support for\n accelerated SMMUv3", "Date": "Wed, 15 Apr 2026 11:55:21 +0100", "Message-ID": "<20260415105552.622421-1-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EE3E:EE_|SJ5PPF8AECCE022:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1f551248-af9f-4bf9-5bec-08de9addb885", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|36860700016|82310400026|1800799024|13003099007|18096099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n T2/Wewn0aFz9dy0q90vkDGtYlk+pRGYVkh7s2ljItElC37/PzqAyB08fkUAxqNw3O6yqXxx2wE1YVdDBY+fjFUFZsyYH4CsCCggVNr5h42YBC15d6n+OL0tedxaiUzm8DAuH0wxEtcgm5WamJoeaIAwEpMp87P+WK3EyUW5AvmHkMp8bf2S/Nv863ZFZAbIoyuAQWHdHYG9nCT2IfdBDcEXshPiPBa2Eoxo+WNwsHFtNAQJYDFc4C7F+TuXsA0Wwos8fyqyt4ME7zvbRWsYg4cOVucffUS8fYL+G5DxrbedRKbx/BJqUb7nZ8bdht1QbaxCag3wBSXBw2ss1w9qJi1MwDlGGVoPT12Gp+ot/X8MAELrzvN9jggjXIvKTagY7ahmdN++mgOdl1tmHwCM+fZUYzhcfzE/FHL8oAEoRfbYL1/tnshF0DhVgnLPS07RAO1MG4GnpFrD9chmXCEv+QlzSlajgmUMIK/XE9ocVeIwMiFM2MmNncNuzZvldsZedbj7ElVisDMVfTjWV66l3QyWwrcpnJZda9j3/eG7afFlCrp9AbbKJrNfg16fVhd9ET5WHfdzF8rIWEzO1imt0iMRBnEQL8mDZTy6Qgqfnv0KOwIBYgCmVn2hkDzgtqNJr05fM3wWI1CiCIx1MFOFc2DgRqPRwX9CpbJ/37+CjPjtnB/TE6ovpjGkCuFtZjqvsWUVFVoiv7w0B6irEo0Bpbhx+1uGfyOIZTgrSg+TPadSFKZ6NddxeX7QybX7ytimH6iUs274LdU8bGWmH6whfrA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(13003099007)(18096099003)(18002099003)(56012099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n P30Ht3T+Ha8a55Y/2cXFfnUyPtpicU3v0nGwsktb1cS9pDrF3QvJ67hsSfF8jBt7gKaGQFvLQ66SsCoJeE3wN0TPp8il3ruqi7TxBeTbeKW3aSFB5UMlUjIavLEIXjSya5a2fr/ObhjfmZiaKQqkuTjD4o0tuTYv5ypEkiKKZv+N/BjrcMnM109gimfhb3fAWe+ElonJm3zgmlNDiFpLJe6nK3Aznq5akK5QTIUy/YG7Ofl2q7v2/mDA7yQqpU18+aqSI/cZpMvqLQqw0aqeNE/FvcGAJk2zhosMJt/LLqLHg3329HCe7XTUyuBbeADJqHsc2WP+TtmTsQKWXiMZi95vgviFSGVkWUfCgA5JyxApbjPxpmqTtLXRiIJpw/s8ImVD5zvzxLN9qfDkc26YbBo9mPsDCV6T9USiceCUggq15bh+5LJHqaME2S9vs4FN", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Apr 2026 10:57:00.6074 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1f551248-af9f-4bf9-5bec-08de9addb885", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EE3E.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ5PPF8AECCE022", "X-Spam_score_int": "-25", "X-Spam_score": "-2.6", "X-Spam_bar": "--", "X-Spam_report": "(-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hi,\n\nChanges from v3:\n https://lore.kernel.org/qemu-devel/20260226105056.897-1-skolothumtho@nvidia.com/\n\n - Addressed v3 feedback and picked up Reviewed-by tags.\n - Folded veventq alloc/free into alloc_viommu/free_viommu, removing\n the separate ops callback (patch 13).\n - Reworked register and macro names based on feedback.\n - Improved documentation around VCMDQ aperture usage, which was a\n source of confusion in v3. See patches 15, 16, 17, 19 and 20.\n Patch 20 in particular explains the cached register vs hardware-backed\n MMIO model for VCMDQ apertures. Hope this is clearer and correct now!.\n - Added patch 21 to skip IOMMU mappings for RAM device regions,\n eliminating spurious \"IOMMU_IOAS_MAP failed: Bad address\" warnings\n for the VINTF page0 guest mapping.\n - Updated SMMUv3 identifier property to accommodate the ITS node id\n (patch 27).\n - Removed qtest bios-tables blob patches; node id changes are now\n handled in patch 27.\n - Based on top of Nathan's \"Resolve AUTO properties\" series [0].\n - Added patch 30 to enforce viommu association stability when CMDQV\n is active.\n\nPlease find the complete branch here:\nhttps://github.com/shamiali2008/qemu-master/tree/master-vcmdq-v4-ext\n\nSanity tested on NVIDIA Grace. Further testing in progress.\n\nFeedback and testing are very welcome.\n\nThanks,\nShameer\n[0] https://lore.kernel.org/qemu-devel/20260401010231.4166776-1-nathanc@nvidia.com\n\n---\nBackground(from RFCv1):\nhttps://lore.kernel.org/qemu-devel/20251210133737.78257-1-skolothumtho@nvidia.com/\n\nThanks to Nicolin for the initial patches and testing on which this\nis based.\n\nTegra241 CMDQV extends SMMUv3 by allocating per-VM \"virtual interfaces\"\n(VINTFs), each hosting up to 128 VCMDQs.\n\nEach VINTF exposes two 64KB MMIO pages:\n - Page0 – guest owned control and status registers (directly mapped\n into the VM)\n - Page1 – queue configuration registers (trapped/emulated by QEMU)\n\nUnlike the standard SMMU CMDQ, a guest owned Tegra241 VCMDQ does not\nsupport the full command set. Only a subset, primarily invalidation\nrelated commands, is accepted by the CMDQV hardware. For this reason,\na distinct CMDQV device must be exposed to the guest, and the guest OS\nmust include a Tegra241 CMDQV aware driver to take advantage of the\nhardware acceleration.\n\nVCMDQ support is integrated via the IOMMU_HW_QUEUE_ALLOC mechanism,\nallowing QEMU to attach guest configured VCMDQ buffers to the\nunderlying CMDQV hardware through IOMMUFD. The Linux kernel already\nsupports the full CMDQV virtualisation model via IOMMUFD[0].\n---\n\nNicolin Chen (15):\n backends/iommufd: Update iommufd_backend_get_device_info\n backends/iommufd: Update iommufd_backend_alloc_viommu to allow user\n ptr\n backends/iommufd: Introduce iommufd_backend_alloc_hw_queue\n backends/iommufd: Introduce iommufd_backend_viommu_mmap\n hw/arm/tegra241-cmdqv: Implement CMDQV init\n hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free\n hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region\n hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads\n hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes\n hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV\n hw/arm/tegra241-cmdqv: Allocate HW VCMDQs on base register programming\n hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space\n hw/arm/tegra241-cmdqv: Add reset handler\n hw/arm/tegra241-cmdqv: Limit queue size based on backend page size\n hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT\n\nShameer Kolothum (16):\n system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq\n hw/arm/smmuv3-accel: Introduce CMDQV ops interface\n hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub\n hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle\n hw/arm/virt: Use stored SMMUv3 device list for IORT build\n hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support\n hw/arm/virt: Link SMMUv3 CMDQV resources to platform bus\n system/physmem: Add address_space_is_ram() helper\n hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as VCMDQ backing\n memory: Allow RAM device regions to skip IOMMU mapping\n hw/arm/smmuv3-accel: Introduce common helper for veventq read\n hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors\n hw/arm/smmuv3: Add per-device identifier property\n hw/arm/smmuv3-accel: Introduce helper to query CMDQV type\n hw/arm/smmuv3-accel: Enforce viommu association when CMDQV is active\n hw/arm/smmuv3: Add cmdqv property for SMMUv3 device\n\n hw/arm/smmuv3-accel.h | 29 ++\n hw/arm/tegra241-cmdqv.h | 367 +++++++++++++++\n include/hw/arm/smmuv3.h | 3 +\n include/hw/arm/virt.h | 1 +\n include/system/iommufd.h | 17 +-\n include/system/memory.h | 12 +\n backends/iommufd.c | 64 +++\n hw/arm/smmuv3-accel-stubs.c | 16 +\n hw/arm/smmuv3-accel.c | 187 ++++++--\n hw/arm/smmuv3.c | 15 +\n hw/arm/tegra241-cmdqv-stubs.c | 16 +\n hw/arm/tegra241-cmdqv.c | 817 ++++++++++++++++++++++++++++++++++\n hw/arm/virt-acpi-build.c | 127 ++++--\n hw/arm/virt.c | 37 ++\n hw/vfio/iommufd.c | 4 +-\n hw/vfio/listener.c | 5 +\n system/physmem.c | 11 +\n backends/trace-events | 4 +-\n hw/arm/Kconfig | 5 +\n hw/arm/meson.build | 2 +\n hw/arm/trace-events | 7 +\n 21 files changed, 1666 insertions(+), 80 deletions(-)\n create mode 100644 hw/arm/tegra241-cmdqv.h\n create mode 100644 hw/arm/tegra241-cmdqv-stubs.c\n create mode 100644 hw/arm/tegra241-cmdqv.c" }