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{ "id": 2222470, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2222470/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775959096.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cover.1775959096.git.chao.liu.zevorn@gmail.com>", "list_archive_url": null, "date": "2026-04-12T02:20:17", "name": "[v6,0/7] riscv: add initial sdext support", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/1.2/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775959096.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 499584, "url": "http://patchwork.ozlabs.org/api/1.2/series/499584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584", "date": "2026-04-12T02:20:20", "name": "riscv: add initial sdext support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2222470/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jwFEvjcC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf43.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hi,\n\nThis v6 series is rebased on Alistair's riscv-to-apply.next branch [1].\n\nThe implementation follows RISC-V Debug Specification 1.0 [2].\n\nIt introduces the sdext/sdtrig config bits, DCSR/DPC/DSCRATCH state,\nDebug Mode enter/leave helpers, DRET, EBREAK entry, single-step, and\ntrigger action=debug mode.\n\nTo reduce review load, this series focuses on the Sdext features first.\nThe Debug Module (DM) and related flows will follow in a later series.\n\nChanges in v6:\n- Rebased onto latest riscv-to-apply.next\n\nChanges in v5:\n- Patch 2: removed redundant `cpu->cfg.ext_sdext = false;` in\n riscv_cpu_init() since it's already set to false in MULTI_EXT_CFG_BOOL.\n (Daniel)\n- Patch 7: changed LOG_UNIMP to LOG_GUEST_ERROR for invalid trigger\n action=debug mode when Sdext is not enabled. LOG_UNIMP is reserved\n for unimplemented features, while LOG_GUEST_ERROR is for invalid\n guest actions. (Daniel)\n\nChanges in v4:\n- Fixed linux-user build errors: moved debug_mode/dcsr/dpc/dscratch\n fields inside #ifndef CONFIG_USER_ONLY block in cpu.h, and wrapped\n all code using these fields with proper guards. (Daniel)\n- Updated dependency from single patch (patch 5 only) to patches 1-5\n of Max Chou's \"Add Zvfbfa extension support\" v2 series to avoid\n compilation errors.\n\nChanges in v3:\n- Rebase onto Alistair's riscv-to-apply.next branch.\n- Depend on Max Chou's patch \"target/riscv: Use the tb->cs_bqse as\n the extend tb flags.\" (not included; apply it first) [3].\n- Patch 2: default sdext to false in riscv_cpu_extensions.\n\nChanges in v2:\n- Drop the RHCT expected AML update from this series.\n- Replace the split sdext/sdtrig config bits patch with deprecating the\n 'debug' CPU property.\n- Rebase and update patch subjects to target/riscv prefix.\n\nChanges in v1:\n- Debug Mode entry/exit updates DCSR/DPC and restores execution via DRET.\n- EBREAK honors DCSR ebreak bits and enters Debug Mode when enabled.\n- Single-step uses DCSR.STEP with a TB flag and a helper at TB exit.\n It references Max Chou's patch \"target/riscv: Use the tb->cs_bqse as\n the extend tb flags.\" [3].\n- Sdtrig supports action=debug mode for mcontrol/mcontrol6 and reports\n inst-count triggers in tinfo.\n\n---\n\nDifferences vs Debug Spec (known gaps):\n- No Debug Module (no DMI, dmcontrol/dmstatus, haltreq/resumereq).\n- No debug ROM, program buffer, abstract commands, or SBA.\n- Resume is modeled by leaving Debug Mode at cpu_exec_enter.\n- Step/exception ordering is simplified: if the stepped instruction\n traps, the normal exception is taken and Debug Mode is not forced.\n- Several DCSR fields are not fully modeled (stopcount/stoptime, etc).\n\nRoadmap (next stage, DM focus):\n1) Add a DM core with DMI access and hart state tracking.\n2) Implement halt/resume handshake and move Debug Mode transitions\n under DM control.\n3) Add debug ROM, program buffer, and abstract commands for GPR/CSR\n and memory access.\n4) Add SBA if required by tooling.\n5) Tighten ordering rules for step/exception/trigger priorities.\n\nCI (all jobs passed except check-patch which flags pre-existing\nupstream style issues, not related to this series) [4].\n\nReferences:\n[1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next\n[2] https://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n[3] https://lore.kernel.org/qemu-devel/20260108132631.9429-1-max.chou@sifive.com/\n[4] https://gitlab.com/TaoTang/qemu/-/pipelines/2446308835\n\n\nThanks,\nChao\n\nChao Liu (6):\n target/riscv: add sdext debug CSRs state\n target/riscv: add sdext Debug Mode helpers\n target/riscv: add dret instruction\n target/riscv: add sdext enter Debug Mode on ebreak\n target/riscv: add sdext single-step support\n target/riscv: add sdtrig trigger action=debug mode\n\nDaniel Henrique Barboza (1):\n target/riscv: deprecate 'debug' CPU property\n\n docs/about/deprecated.rst | 7 +\n include/exec/translation-block.h | 4 +-\n target/riscv/cpu.c | 59 +++++++-\n target/riscv/cpu.h | 9 ++\n target/riscv/cpu_bits.h | 33 +++++\n target/riscv/cpu_cfg_fields.h.inc | 3 +-\n target/riscv/cpu_helper.c | 90 ++++++++++++\n target/riscv/csr.c | 128 +++++++++++++++++-\n target/riscv/debug.c | 58 +++++++-\n target/riscv/helper.h | 3 +\n target/riscv/insn32.decode | 1 +\n .../riscv/insn_trans/trans_privileged.c.inc | 24 ++++\n target/riscv/machine.c | 44 ++++--\n target/riscv/op_helper.c | 70 ++++++++++\n target/riscv/tcg/tcg-cpu.c | 21 ++-\n target/riscv/translate.c | 15 +-\n 16 files changed, 544 insertions(+), 25 deletions(-)" }