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{ "id": 2221556, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2221556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260409185254.3869808-1-zhiw@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260409185254.3869808-1-zhiw@nvidia.com>", "list_archive_url": null, "date": "2026-04-09T18:52:53", "name": "[0/1] Rust PCI capability infrastructure and SR-IOV support", "submitter": { "id": 88076, "url": "http://patchwork.ozlabs.org/api/1.2/people/88076/?format=api", "name": "Zhi Wang", "email": "zhiw@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260409185254.3869808-1-zhiw@nvidia.com/mbox/", "series": [ { "id": 499342, "url": "http://patchwork.ozlabs.org/api/1.2/series/499342/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499342", "date": "2026-04-09T18:52:54", "name": "Rust PCI capability infrastructure and SR-IOV support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499342/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2221556/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-52228-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=altIpzUc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Zhi Wang <zhiw@nvidia.com>", "To": "<rust-for-linux@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "<dakr@kernel.org>, <aliceryhl@google.com>, <bhelgaas@google.com>,\n\t<kwilczynski@kernel.org>, <ojeda@kernel.org>, <boqun@kernel.org>,\n\t<gary@garyguo.net>, <bjorn3_gh@protonmail.com>, <lossin@kernel.org>,\n\t<a.hindborg@kernel.org>, <tmgross@umich.edu>, <markus.probst@posteo.de>,\n\t<cjia@nvidia.com>, <smitra@nvidia.com>, <ankita@nvidia.com>,\n\t<aniketa@nvidia.com>, <kwankhede@nvidia.com>, <targupta@nvidia.com>,\n\t<acourbot@nvidia.com>, <joelagnelf@nvidia.com>, <jhubbard@nvidia.com>,\n\t<kjaju@nvidia.com>, <zhiwang@kernel.org>, Zhi Wang <zhiw@nvidia.com>", "Subject": "[PATCH 0/1] Rust PCI capability infrastructure and SR-IOV support", "Date": "Thu, 9 Apr 2026 21:52:53 +0300", "Message-ID": "<20260409185254.3869808-1-zhiw@nvidia.com>", "X-Mailer": "git-send-email 2.51.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D1:EE_|DS5PPFA33D606F8:EE_", "X-MS-Office365-Filtering-Correlation-Id": "02c7b58c-3185-454c-6783-08de966945a9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|7416014|1800799024|36860700016|376014|13003099007|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\ttjU6uacTAtfnziRV/hEFrmyYE+yaBwLIl+0sJ+8rjy3FCyJQzIock9DRu6IaJH1xbFgo+v9kqQTwqFl4JpbenNXo2Iz7lBBQa/gPYRyP5zQZ9RFaLLiY9lRmcphE/BEHjDEh3/4kEUVHz8Gtb7rIFigZhflXobyyRAx1KpZrlYWTj6YaOohFLv8pWD3GMscGB+Oy6y6RypcAqe1dALaohCGe1f1C1F4RwoynfYg066yZ4pBpQG+1x3U/niHCwgN6DaVzPD8tknZdg4FGIa1jHhLB4gFgt1pIi7lli9XoMLpJNC50pggNUl7SPsBIaC6mWEIYZ+qwzTTyV5KJd5X4EHqZxS4BudoWYvn2ST7B2fyNBEl0mQoQfkqNqzSboUzAXW0SDtMJJCMRBAueg0ogAyUY3BiHm4ZrFmuTR8qcxzfnBMAwq+L4+k2o3wh0oy3M7SiU9XDF2+VVgYNRDrEbUWXE41v4NjuVnXMdMsZbrGaeBIiLOqWpxuMQVT0kAoz5PBae0lZIL4Pa6rWP7sK4bGuG7nhYHEK8qlKgtJHx/ie3xyrOt2cQ/N9nVSGz3Ia81mTBnV4OPf+66JzSlwln5U8uKpHOjYuSsIafTVmUxzbJm4+X0pN478eSbgq7L8qOLG+5L08LPXs6GPjVurM6dnxwwOzgf7AHCBb+6Rkh8rSEBUbTZs8XyajpcRelPCJyYpcKASoK7s46VbZZyDcEPqEl+MEoXNsploquUoH6epN9GQH46RLaHX4KVxGx3/DP84NxUfnpVGTN1be/aF+rEw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(1800799024)(36860700016)(376014)(13003099007)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tifygGT+cOqZMs8iHNVfBxMq49KrbEqQ57IJ4PACnDXC1kEPpKGzs26oP/8au4MYRSe4HuGKxY26G9cd3Iq3RFOD7tevMvDFUP8N/Ev7phDe5DFenKikf246pVpp8ynImYlLQQjKFxBKvUVXSQdAR0Z1cUlCd0h1kzYpBgoBWOZoH9rIr0WaXXdl3u1QfuVjbDCTiDETDybkOzboEjFZ1GZTeNNZAB3AWPi0596Hwy0dEQGBk+Pz+zi7Y4PvmfZi0w7JyTmMzBP6YHeTDZ5ZiQQ8Sdrk/N64/plltFdwof9HyBKM05ha115in9bW80IRJO3vbR3r3UlqIQqMHuJ+KHhPYLTPTfWuXRTNmEEB18kabTYA6H9e3xXHBvzeOJcXT7w4Dokiexsi55hJvrsqjagAaZd+PI0mxZAY6i6SsXwfVxSXHPoSsGHrG2ygp/vAF", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Apr 2026 18:53:21.6255\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 02c7b58c-3185-454c-6783-08de966945a9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000E9D1.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS5PPFA33D606F8" }, "content": "This is a follow-up to the RFC v2 series [1], reworked on top of Gary's\nio_projection patches [2] to use the Io/IoCapable/View infrastructure.\n\nThis patch has been used in Boot GSP with vGPU enabled series [3].\n\nThis patch introduces ExtCapability<T>, which implements the Io trait\nfor PCI extended capability regions. It delegates IoCapable to the\nunderlying ConfigSpace, so io_project!/io_read!/io_write! work directly\non capability register structs. ExtSriovRegs provides the #[repr(C)]\nSR-IOV register layout, and ExtSriovCapability is a convenience alias.\n\nChanges since RFC v2:\n- Hardened calculate_ext_cap_size() against corrupt capability lists.\n- Added // INVARIANT: comments at all ExtCapability construction sites\n (make_ext_capability and cast_sized).\n- Added #[inline] to small forwarding methods (find, read_vf_bar64)\n\nChanges since RFC:\n- Rebased on io_projection branch, using Gary's Io/IoCapable traits\n- ExtCapability implements Io and delegates IoCapable to ConfigSpace\n instead of duplicating config read/write logic\n- Dropped the fallible I/O patch (now upstream in this tree)\n- Added rust helper for PCI_EXT_CAP_NEXT() macro\n- Replaced raw `as` casts with From conversions where possible\n- Renamed SriovRegs/SriovCapability to ExtSriovRegs/ExtSriovCapability\n\n[1] https://lore.kernel.org/rust-for-linux/20260225180449.1813833-1-zhiw@nvidia.com/\n[2] https://lore.kernel.org/rust-for-linux/20260323153807.1360705-1-gary@kernel.org/\n[3] https://lore.kernel.org/rust-for-linux/20260313165336.935771-1-zhiw@nvidia.com/\n\nZhi Wang (1):\n rust: pci: add extended capability and SR-IOV support\n\n rust/helpers/pci.c | 5 +\n rust/kernel/pci.rs | 7 ++\n rust/kernel/pci/cap.rs | 256 +++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 268 insertions(+)\n create mode 100644 rust/kernel/pci/cap.rs\n\n\nbase-commit: 016f794f04888a304322c746b0a7794888d86e21" }