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{ "id": 2220928, "url": "http://patchwork.ozlabs.org/api/1.2/covers/2220928/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/cover/20260408121841.186410-1-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260408121841.186410-1-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-08T12:18:34", "name": "[v4,0/7] qcom: Add NVMEM bitfield support and reboot���mode integration", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/1.2/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/cover/20260408121841.186410-1-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 499133, "url": "http://patchwork.ozlabs.org/api/1.2/series/499133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499133", "date": "2026-04-08T12:18:34", "name": "qcom: Add NVMEM bitfield support and reboot���mode integration", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499133/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2220928/comments/", "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=gKER89s+;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=FCm33g8G;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"gKER89s+\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"FCm33g8G\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frMbN2jF6z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 22:20:32 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 70DDE83D8A;\n\tWed, 8 Apr 2026 14:20:24 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 5C97A8407E; Wed, 8 Apr 2026 14:20:23 +0200 (CEST)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id AB931838BB\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 14:20:20 +0200 (CEST)", "from pps.filterd (m0279867.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 638B3g2v249516\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 12:20:19 GMT", "from mail-pg1-f197.google.com (mail-pg1-f197.google.com\n [209.85.215.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dd8x9b2h1-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 12:20:18 +0000 (GMT)", "by mail-pg1-f197.google.com with SMTP id\n 41be03b00d2f7-c76bd4feb9fso2530713a12.0\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 05:20:18 -0700 (PDT)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 cv=Rr716imK c=1 sm=1 tr=0 ts=69d64802 cx=c_pps\n a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=wgel_GvmafDJSgGvLScA:9 a=QEXdDO2ut3YA:10\n a=bFCP_H2QrGi7Okbo017w:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA4MDExMiBTYWx0ZWRfX9rIPOijeCsS/\n p/DeejEScWOU9GpomElVkUtOJVmGDiYi2jVs3EuZXY6Y1nEYW6cSMMWA6hD0TROKrV03WkNqnv5\n VfNiTCKDuBNvJlzbmE0W+oAzuu89IDwlHOALFxNkfwy5y0EhcYKDz+5evh/Jly9DbZYXdlrOaUY\n CBLSvLoUrP0yJ/sNuuV+hKZmii8sjJ+cP9otzt0Esfa1PYy6L34k+Y2KOOAuQsJlZaud/SXQpFb\n ZcG9ImH8VIE1SYnfga1ozhkE6qS6lLPbADzKXxAKrnBthRU/L4OnK5keZP0A4juEfMj4JUCCZxC\n 9VPkTWd5X4uccfJbMFW9FlwbnU9ArPZi7d9qrrkC80We8lVWhkk4u+UlhZfnW4OFg5C1fCvqkTz\n NK38ZG5t8ubAxleGLZ1i19+EzL6SA6WnAiRATlvSAXkZv7oE7gGZR+01J6uEoEdOYtbHHYeQpt4\n BrBUvgvmHLZn2q87Mtg==", "X-Proofpoint-ORIG-GUID": "Zz-e8sYIgK_wSOJno10PqV1trsQhxiKX", "X-Proofpoint-GUID": "Zz-e8sYIgK_wSOJno10PqV1trsQhxiKX", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 priorityscore=1501 suspectscore=0 malwarescore=0\n clxscore=1015 bulkscore=0 phishscore=0 adultscore=0 spamscore=0\n lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000\n definitions=main-2604080112", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This patch series introduces bit-level granularity to NVMEM cells and\nadds complete reboot-mode support for Qualcomm platforms that store\nreboot reasons in PMIC registers.\n\nQualcomm SoCs rely on PMIC-backed reboot reason storage to implement\nfeatures like \"reboot bootloader\" for entering fastboot mode. However,\nthese PMIC registers often pack multiple fields into a single byte,\nrequiring fine-grained bit access that the current NVMEM subsystem does\nnot support.\n\nIn addition, PMIC generations differ in how reboot-related data is\nstored: older PMICs use PON (Power On) registers, while newer ones\nprovide SDAM regions. This series introduces a unified, NVMEM-based\napproach that works seamlessly across both architectures.\n\nThis version also integrates reboot-mode handling into Qualcomm board\ninitialization, enabling automatic fastboot entry when the reboot reason\nindicates bootloader mode.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n\n---\nChanges in v4:\n1. NVMEM Core (drivers/misc/nvmem.c, include/nvmem.h):\n\n- Explicitly interpret hardware bytes as little-endian for bitfield operations\n to ensure consistent behavior across architectures\n- Removed const pointer write violation in nvmem_cell_write()\n- Replaced unsafe bit shift expressions with GENMASK() macro to avoid undefined\n behavior when nbits == 32\n- Consolidated size validation logic for clarity\n- Enhanced documentation with explicit @cell parameters (offset, size, nbits, bit_offset)\n- Changed magic number 4 to sizeof(u32) for consistency\n\n2. QCOM SPMI SDAM Driver (drivers/misc/qcom-spmi-sdam.c):\n\n- Fixed address type mismatch using local fdt_addr_t variable to prevent silent\n comparison failure on 64-bit platforms\n- Removed non-standard qcom,sdam-size property and hardcoded SDAM size to 0x100\n bytes per hardware specification\n- Changed dev_info() to dev_dbg() to reduce boot log verbosity\n\n3. Board Integration (arch/arm/mach-snapdragon/board.c):\n\n- Simplified conditional compilation with runtime check instead of #ifdef wrapper\n- Adopted logging subsystem (log_info/log_warning) consistent with rest of file\n- Added error handling for fastboot command failures\n\n4. Device Tree (arch/arm/dts/qcs615-ride-u-boot.dtsi):\n\n- Changed bits property to decimal format (bits = <1 7>) for consistency with\n upstream conventions\n\n5. Test Coverage (test/dm/nvmem.c):\n\n- Created separate test file for NVMEM bitfield tests\n- Fixed test to use correct I2C EEPROM functions\n- Corrected test expectation bug for 4-byte cell with 12-bit field spanning byte boundary\n- Added comprehensive error validation tests\n\nLink to v3:\nhttps://lore.kernel.org/u-boot/20260330171419.1117817-1-aswin.murugan@oss.qualcomm.com/\n\nChanges in v3:\n1. Simplified bit field handling to maximum u32 size (32 bits).\n2. Enforced strict size matching (size == cell->size) when nbits == 0.\n3. Enhanced test function for NVMEM read & write\n4. Updated NVMEM API documentation\n\nLink to v2:\nhttps://lore.kernel.org/all/20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com/\n\nChanges in v2:\n1. Replaced custom reboot reason handling with the standard U-Boot\n reboot-mode subsystem, per review feedback.\n2. Added bit-field support to the NVMEM core using the new \"bits\"\n property.\n3. Introduced the Qualcomm SPMI SDAM driver for unified PMIC storage\n access.\n4. Updated the reboot-mode driver to support variable-sized NVMEM cells.\n5. Added device tree configuration for the QCS615 RIDE board.\n6. Enabled reboot-mode in qcom_defconfig.\n7. Integrated reboot-mode detection into Snapdragon board\n initialization:\n - Added qcom_handle_reboot_mode() in board_late_init() to enable\n automatic fastboot entry on \"reboot bootloader\".\n\nLink to v1:\nhttps://lore.kernel.org/all/20260108065533.1143179-1-aswin.murugan@oss.qualcomm.com/\n\n---\n\nAswin Murugan (7):\n misc: Add support for bit fields in NVMEM cells\n misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver\n mach-snapdragon: Integrate reboot-mode handling\n dts: qcs615-ride-u-boot.dtsi: Add reboot-mode support\n qcom_defconfig: Enable reboot-mode support in qcom_defconfig\n test: dm: add comprehensive tests for NVMEM bit field operations\n misc: update API documentation for bit field support in NVMEM\n\n arch/arm/dts/qcs615-ride-u-boot.dtsi | 26 ++++\n arch/arm/mach-snapdragon/board.c | 59 ++++++--\n arch/sandbox/dts/test.dts | 12 ++\n configs/qcom_defconfig | 3 +\n drivers/misc/Kconfig | 8 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/nvmem.c | 166 +++++++++++++++++++---\n drivers/misc/qcom-spmi-sdam.c | 202 +++++++++++++++++++++++++++\n include/nvmem.h | 40 +++++-\n test/dm/Makefile | 1 +\n test/dm/nvmem.c | 160 +++++++++++++++++++++\n 11 files changed, 641 insertions(+), 37 deletions(-)\n create mode 100644 drivers/misc/qcom-spmi-sdam.c\n create mode 100644 test/dm/nvmem.c" }