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GET /api/1.1/patches/2233432/?format=api
{ "id": 2233432, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2233432/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260506123507.2081751-12-mwalle@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260506123507.2081751-12-mwalle@kernel.org>", "date": "2026-05-06T12:34:20", "name": "[v2,11/11] p2041rdb: convert README to rst", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b45332716dde6b8a1c0018db64569b1c17a7721", "submitter": { "id": 86646, "url": "http://patchwork.ozlabs.org/api/1.1/people/86646/?format=api", "name": "Michael Walle", "email": "mwalle@kernel.org" }, "delegate": { "id": 55230, "url": "http://patchwork.ozlabs.org/api/1.1/users/55230/?format=api", "username": "freenix", "first_name": "Peng", "last_name": "Fan", "email": "van.freenix@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260506123507.2081751-12-mwalle@kernel.org/mbox/", "series": [ { "id": 502979, "url": "http://patchwork.ozlabs.org/api/1.1/series/502979/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502979", "date": "2026-05-06T12:34:09", "name": "Generic powerpc fixes and NXP board cleanup", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502979/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233432/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233432/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=KYdO167l;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"KYdO167l\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=mwalle@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g9ZfQ1f7yz1yJq\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 06 May 2026 22:37:50 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6997184974;\n\tWed, 6 May 2026 14:36:50 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 6DACD8484F; Wed, 6 May 2026 14:36:49 +0200 (CEST)", "from sea.source.kernel.org (sea.source.kernel.org\n [IPv6:2600:3c0a:e001:78e:0:1991:8:25])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 2D6058497A\n for <u-boot@lists.denx.de>; Wed, 6 May 2026 14:36:46 +0200 (CEST)", "from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58])\n by sea.source.kernel.org (Postfix) with ESMTP id D613143EFC;\n Wed, 6 May 2026 12:36:44 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id EF27EC2BCB8;\n Wed, 6 May 2026 12:36:40 +0000 (UTC)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1778071004;\n bh=cr/NRii/FbqTCDZx0egkUlp2RqZnM00KqvE7rTxF+xo=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=KYdO167lw4asTnwgevATWEwAM/TQMT7cKhJvWnekuL1Z5cwpc3k49fer/7wRNSzq3\n 6Koizb+nlJhSM/ltdxSDN7VsRBCo+KSd49pqXAdDIFRs5SF3YnkVDrKULT2TaYG8cV\n hnIg9k4ZC2m8OgeaC4D5adn3QIjaLmo3UXdFrDcuPRUc2xivOHr2BwFxOvzu2WHEn+\n Zig85UnGg8CKoLmC6uWBfOJTUvaz/eNWbjG7tZF49fz/aoCJplsVrr28UsF3t1kCPa\n qktCwZiNqGm5Got+5UbgqOaPuvmnqDDPjbFos7er2fjyi5ROg4EDtJOPYNviK0PQqk\n h8S+BI+1xdjFQ==", "From": "Michael Walle <mwalle@kernel.org>", "To": "=?utf-8?q?Marek_Beh=C3=BAn?= <kabel@kernel.org>,\n Tom Rini <trini@konsulko.com>, Pramod Kumar <pramod.kumar_1@nxp.com>,\n Vladimir Oltean <olteanv@gmail.com>, Alison Wang <alison.wang@nxp.com>,\n Tang Yuantian <andy.tang@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n Priyanka Jain <priyanka.jain@nxp.com>, Wasim Khan <wasim.khan@nxp.com>,\n Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,\n TsiChung Liew <Tsi-Chung.Liew@nxp.com>, Stefano Babic <sbabic@nabladev.com>,\n Fabio Estevam <festevam@gmail.com>,\n \"NXP i . MX U-Boot Team\" <uboot-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,\n Shengzhou Liu <Shengzhou.Liu@nxp.com>", "Cc": "Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>,\n Jerome Forissier <jerome.forissier@arm.com>, u-boot@lists.denx.de,\n Michael Walle <mwalle@kernel.org>", "Subject": "[PATCH v2 11/11] p2041rdb: convert README to rst", "Date": "Wed, 6 May 2026 14:34:20 +0200", "Message-ID": "<20260506123507.2081751-12-mwalle@kernel.org>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260506123507.2081751-1-mwalle@kernel.org>", "References": "<20260506123507.2081751-1-mwalle@kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Convert the README to reST format.\n\nSigned-off-by: Michael Walle <mwalle@kernel.org>\n---\n board/nxp/p2041rdb/README | 128 -----------------------------\n board/nxp/p2041rdb/README.rst | 147 ++++++++++++++++++++++++++++++++++\n 2 files changed, 147 insertions(+), 128 deletions(-)\n delete mode 100644 board/nxp/p2041rdb/README\n create mode 100644 board/nxp/p2041rdb/README.rst", "diff": "diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README\ndeleted file mode 100644\nindex c2a2f0ed9e5..00000000000\n--- a/board/nxp/p2041rdb/README\n+++ /dev/null\n@@ -1,128 +0,0 @@\n-Overview\n-=========\n-The P2041 Processor combines four Power Architecture processor cores\n-with high-performance datapath acceleration architecture(DPAA), CoreNet\n-fabric infrastructure, as well as network and peripheral bus interfaces\n-required for networking, telecom/datacom, wireless infrastructure, and\n-military/aerospace applications.\n-\n-P2041RDB board is a quad core platform supporting the P2041 processor\n-of QorIQ DPAA series.\n-\n-Boot from NOR flash\n-===================\n-1. Build image\n-\tmake P2041RDB_config\n-\tmake all\n-\n-2. Program image\n-\t=> tftp 1000000 u-boot.bin\n-\t=> protect off all\n-\t=> erase eff40000 efffffff\n-\t=> cp.b 1000000 eff40000 c0000\n-\n-3. Program RCW\n-\t=> tftp 1000000 rcw.bin\n-\t=> protect off all\n-\t=> erase e8000000 e801ffff\n-\t=> cp.b 1000000 e8000000 50\n-\n-4. Program FMAN Firmware ucode\n-\t=> tftp 1000000 ucode.bin\n-\t=> protect off all\n-\t=> erase eff00000 eff3ffff\n-\t=> cp.b 1000000 eff00000 2000\n-\n-5. Change DIP-switch\n-\tSW1[1-5] = 10110\n-\tNote: 1 stands for 'on', 0 stands for 'off'\n-\n-Boot from SDCard\n-===================\n-1. Build image\n-\tmake P2041RDB_SDCARD_config\n-\tmake all\n-\n-2. Program the PBL image to SDCard\n-\t=> tftp 1000000 u-boot.pbl\n-\t=> mmc info\n-\t=> mmc write 1000000 8 672\n-\n-3. Program FMAN Firmware ucode\n-\t=> tftp 1000000 ucode.bin\n-\t=> mmc write 1000000 690 10\n-\n-4. Change DIP-switch\n-\tSW1[1-5] = 01100\n-\tNote: 1 stands for 'on', 0 stands for 'off'\n-\n-Boot from SPI flash\n-===================\n-1. Build image\n-\tmake P2041RDB_SPIFLASH_config\n-\tmake all\n-\n-2. Program the PBL image to SPI flash\n-\t=> tftp 1000000 u-boot.pbl\n-\t=> sf probe 0\n-\t=> sf update $fileaddr 0 $filesize\n-\n-3. Program FMAN Firmware ucode\n-\t=> tftp 1000000 ucode.bin\n-\t=> sf update $fileaddr 110000 $filesize\n-\n-4. Change DIP-switch\n-\tSW1[1-5] = 10100\n-\tNote: 1 stands for 'on', 0 stands for 'off'\n-\n-Device tree support and how to enable it for different configs\n---------------------------------------------------------------\n-Device tree support is available for p2041rdb for below mentioned boot,\n-1. NOR Boot\n-2. NAND Boot\n-3. SD Boot\n-4. SPIFLASH Boot\n-\n-To enable device tree support for other boot, below configs need to be\n-enabled in relative defconfig file,\n-1. CONFIG_DEFAULT_DEVICE_TREE=\"p2041rdb\" (Change default device tree name if required)\n-2. CONFIG_OF_CONTROL\n-3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at\n- CFG_RESET_VECTOR_ADDRESS - 0xffc\n-\n-CPLD command\n-============\n-The CPLD is used to control the power sequence and some serdes lane\n-mux function.\n-\n-cpld reset\t\t\t - hard reset to default bank\n-cpld reset altbank\t\t - reset to alternate bank\n-cpld lane_mux <lane> <mux_value> - set multiplexed lane pin\n-\t\tlane 6: 0 -> slot1 (Default)\n-\t\t\t1 -> SGMII\n-\t\tlane a: 0 -> slot2 (Default)\n-\t\t\t1 -> AURORA\n-\t\tlane c: 0 -> slot2 (Default)\n-\t\t\t1 -> SATA0\n-\t\tlane d: 0 -> slot2 (Default)\n-\t\t\t1 -> SATA1\n-\n-Using the Device Tree Source File\n-=================================\n-To create the DTB (Device Tree Binary) image file, use a command\n-similar to this:\n-\tdtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb\n-\n-Or use the following command:\n-\t{linux-2.6}/make p2041rdb.dtb ARCH=powerpc\n-\n-then the dtb file will be generated under the following directory:\n-\t{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb\n-\n-Booting Linux\n-=============\n-Place a linux uImage in the TFTP disk area.\n-\ttftp 1000000 uImage\n-\ttftp 2000000 rootfs.ext2.gz.uboot\n-\ttftp 3000000 p2041rdb.dtb\n-\tbootm 1000000 2000000 3000000\ndiff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst\nnew file mode 100644\nindex 00000000000..8b8214adc57\n--- /dev/null\n+++ b/board/nxp/p2041rdb/README.rst\n@@ -0,0 +1,147 @@\n+.. SPDX-License-Identifier: GPL-2.0\n+\n+P2041-RDB Board Overview\n+========================\n+\n+The P2041 Processor combines four Power Architecture processor cores\n+with high-performance datapath acceleration architecture(DPAA), CoreNet\n+fabric infrastructure, as well as network and peripheral bus interfaces\n+required for networking, telecom/datacom, wireless infrastructure, and\n+military/aerospace applications.\n+\n+P2041RDB board is a quad core platform supporting the P2041 processor\n+of QorIQ DPAA series.\n+\n+Boot from NOR flash\n+===================\n+\n+1. Build image::\n+\n+ make P2041RDB_config\n+ make all\n+\n+2. Program image::\n+\n+ => tftp 1000000 u-boot.bin\n+ => protect off all\n+ => erase eff40000 efffffff\n+ => cp.b 1000000 eff40000 c0000\n+\n+3. Program RCW::\n+\n+ => tftp 1000000 rcw.bin\n+ => protect off all\n+ => erase e8000000 e801ffff\n+ => cp.b 1000000 e8000000 50\n+\n+4. Program FMAN Firmware ucode::\n+\n+ => tftp 1000000 ucode.bin\n+ => protect off all\n+ => erase eff00000 eff3ffff\n+ => cp.b 1000000 eff00000 2000\n+\n+5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off'\n+\n+Boot from SDCard\n+================\n+\n+1. Build image::\n+\n+ make P2041RDB_SDCARD_config\n+ make all\n+\n+2. Program the PBL image to SDCard::\n+\n+ => tftp 1000000 u-boot.pbl\n+ => mmc info\n+ => mmc write 1000000 8 672\n+\n+3. Program FMAN Firmware ucode::\n+\n+ => tftp 1000000 ucode.bin\n+ => mmc write 1000000 690 10\n+\n+4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off'\n+\n+Boot from SPI flash\n+===================\n+\n+1. Build image::\n+\n+ make P2041RDB_SPIFLASH_config\n+ make all\n+\n+2. Program the PBL image to SPI flash::\n+\n+ => tftp 1000000 u-boot.pbl\n+ => sf probe 0\n+ => sf update $fileaddr 0 $filesize\n+\n+3. Program FMAN Firmware ucode::\n+\n+ => tftp 1000000 ucode.bin\n+ => sf update $fileaddr 110000 $filesize\n+\n+4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off'\n+\n+Device tree support and how to enable it for different configs\n+--------------------------------------------------------------\n+\n+Device tree support is available for p2041rdb for below mentioned boot,\n+\n+1. NOR Boot\n+2. NAND Boot\n+3. SD Boot\n+4. SPIFLASH Boot\n+\n+To enable device tree support for other boot, below configs need to be\n+enabled in relative defconfig file,\n+\n+1. CONFIG_DEFAULT_DEVICE_TREE=\"p2041rdb\" (Change default device tree name if required)\n+2. CONFIG_OF_CONTROL\n+3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at\n+ CFG_RESET_VECTOR_ADDRESS - 0xffc\n+\n+CPLD command\n+============\n+\n+The CPLD is used to control the power sequence and some serdes lane\n+mux function::\n+\n+ cpld reset\t\t\t - hard reset to default bank\n+ cpld reset altbank\t\t - reset to alternate bank\n+ cpld lane_mux <lane> <mux_value> - set multiplexed lane pin\n+ lane 6: 0 -> slot1 (Default)\n+ 1 -> SGMII\n+ lane a: 0 -> slot2 (Default)\n+ 1 -> AURORA\n+ lane c: 0 -> slot2 (Default)\n+ 1 -> SATA0\n+ lane d: 0 -> slot2 (Default)\n+ 1 -> SATA1\n+\n+Using the Device Tree Source File\n+=================================\n+To create the DTB (Device Tree Binary) image file, use a command\n+similar to this::\n+\n+ dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb\n+\n+Or use the following command::\n+\n+ {linux-2.6}/make p2041rdb.dtb ARCH=powerpc\n+\n+then the dtb file will be generated under the following directory::\n+\n+ {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb\n+\n+Booting Linux\n+=============\n+\n+Place a linux uImage in the TFTP disk area::\n+\n+ => tftp 1000000 uImage\n+ => tftp 2000000 rootfs.ext2.gz.uboot\n+ => tftp 3000000 p2041rdb.dtb\n+ => bootm 1000000 2000000 3000000\n", "prefixes": [ "v2", "11/11" ] }