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GET /api/1.1/patches/2233383/?format=api
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{
    "id": 2233383,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2233383/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/20260506053801.3433002-1-zombie12139@gmail.com/",
    "project": {
        "id": 41,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/41/?format=api",
        "name": "GNU C Library",
        "link_name": "glibc",
        "list_id": "libc-alpha.sourceware.org",
        "list_email": "libc-alpha@sourceware.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260506053801.3433002-1-zombie12139@gmail.com>",
    "date": "2026-05-06T05:38:01",
    "name": "x86: Fix non-temporal memset unreachable on AMD Zen 3/4/5",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "efd71329f66952136a4cc019d3a92e5df43dea81",
    "submitter": {
        "id": 93341,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/93341/?format=api",
        "name": "zombie12138",
        "email": "zombie12139@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/20260506053801.3433002-1-zombie12139@gmail.com/mbox/",
    "series": [
        {
            "id": 502958,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/502958/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=502958",
            "date": "2026-05-06T05:38:01",
            "name": "x86: Fix non-temporal memset unreachable on AMD Zen 3/4/5",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/502958/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2233383/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2233383/checks/",
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        "From": "zombie12138 <zombie12139@gmail.com>",
        "To": "libc-alpha@sourceware.org",
        "Cc": "goldstein.w.n@gmail.com, hjl.tools@gmail.com,\n zombie12138 <zombie12139@gmail.com>",
        "Subject": "[PATCH] x86: Fix non-temporal memset unreachable on AMD Zen 3/4/5",
        "Date": "Tue,  5 May 2026 22:38:01 -0700",
        "Message-ID": "<20260506053801.3433002-1-zombie12139@gmail.com>",
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        "Errors-To": "libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org"
    },
    "content": "On AMD Zen 3/4/5 with ERMS, the non-temporal memset path is unreachable\nbecause rep_stosb_threshold is set to SIZE_MAX (vectorized loop is faster\nthan ERMS on these CPUs), but the non-temporal code path is nested inside\nthe rep_stosb branch.\n\nThe existing rescue logic at the Avoid_STOSB check only covers the case\nwhere the CPU lacks ERMS hardware support.  It does not cover AMD Zen 3+\nwhere ERMS is supported but deliberately unused for performance reasons.\n\nExtend the condition to also lower rep_stosb_threshold when:\n- The user has not explicitly set x86_rep_stosb_threshold (respect tunables)\n- rep_stosb_threshold is higher than memset_non_temporal_threshold (NT gated)\n\nThis makes the non-temporal path reachable for large memset operations,\nproviding ~2x speedup on pre-faulted buffers larger than L3 cache.\n\nTested on AMD Ryzen 7 8745HS (Zen 4):\n- Pre-faulted 64MB memset: 2.02 ms -> 0.94 ms (2.15x faster)\n- First-touch 64MB memset: 19.3 ms -> 21.3 ms (11% regression, expected:\n  kernel clear_page cache warming bypassed by NT stores)\n\n\t* sysdeps/x86/dl-cacheinfo.h (dl_init_cacheinfo): Extend\n\trep_stosb_threshold lowering condition to cover AMD Zen 3/4/5\n\twhere ERMS is supported but stosb is disabled via threshold.\n\nSigned-off-by: zombie12138 <zombie12139@gmail.com>\nBug: https://sourceware.org/bugzilla/show_bug.cgi?id=34129\n---\n sysdeps/x86/dl-cacheinfo.h | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h\nindex b6e17b0e32..78929d1f2d 100644\n--- a/sysdeps/x86/dl-cacheinfo.h\n+++ b/sysdeps/x86/dl-cacheinfo.h\n@@ -1293,7 +1293,9 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)\n   /* Do `rep_stosb_thresh = non_temporal_thresh` after setting/getting the\n      final value of `x86_memset_non_temporal_threshold`. In some cases this can\n      be a matter of correctness.  */\n-  if (CPU_FEATURES_ARCH_P (cpu_features, Avoid_STOSB))\n+  if (CPU_FEATURES_ARCH_P (cpu_features, Avoid_STOSB)\n+      || (!TUNABLE_IS_INITIALIZED (x86_rep_stosb_threshold)\n+\t  && rep_stosb_threshold > memset_non_temporal_threshold))\n     rep_stosb_threshold\n \t= TUNABLE_GET (x86_memset_non_temporal_threshold, long int, NULL);\n   TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1,\n",
    "prefixes": []
}