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GET /api/1.1/patches/2233354/?format=api
{ "id": 2233354, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2233354/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260506094623.29327-7-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260506094623.29327-7-fengchengwen@huawei.com>", "date": "2026-05-06T09:46:23", "name": "[v6,6/6] vfio/pci: Add PCIe TPH SET_ST interface", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5a6cf655358bc68107b18b845600f30757bcbb1c", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.1/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260506094623.29327-7-fengchengwen@huawei.com/mbox/", "series": [ { "id": 502946, "url": "http://patchwork.ozlabs.org/api/1.1/series/502946/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502946", "date": "2026-05-06T09:46:19", "name": "vfio/pci: Add PCIe TPH support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/502946/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233354/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233354/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53842-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=M65/ug89;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53842-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"M65/ug89\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.227", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g9Vzn5djdz1yJx\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 06 May 2026 19:52:37 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id BD209305090A\n\tfor <incoming@patchwork.ozlabs.org>; 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Wed, 6 May 2026 17:46:32 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778060796; cv=none;\n b=LXPYoNaafcWsn2Nrri7gtaSgfWi45CxL+3dNRem41A9PTG9oOp7M9GBR1s9v3Efl3pqIh2CHRCVFaJ3Qo2IkQJ2Bd99ZTP6LyLa6zHr2B4JS1l0eNUjSZb8gNxuYCud1x9Aa8hcWxaEBmmZSbM9cTlGy3VgxCkalDgXMJKz+ugE=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778060796; c=relaxed/simple;\n\tbh=WsOIECMjZHArg93ZhDA7Q1Pqj/DC1q0aPGMD5VerzOI=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=EI7Y27eDj8JjDxDM9UI1OV5kKtZjnHhJJYSOqssURsX583NDc+FOntm+zvN/5lXoDw4FeLmsmsQ2BINIfVLt61UT1asGDZtAZXoX0F8x4N4xeHPb5H8zgAOoleU944HKmSbjnT+Rnpv14Hce0FDLMQAoanABqyQNgU4ErSqNSL4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=M65/ug89; arc=none smtp.client-ip=113.46.200.227", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=x8UZ9NZJFRwtYskhmwUWiRqPY8vaq2K0ttl4pxpMomU=;\n\tb=M65/ug89S/D/Z3Dw+aPjBWtaEWfYojqgSYpvzEQFu9CNXjEusPAQvdHHcKTCWXl6fsSrrjjDl\n\t2AHTZUkhoSpVFrxfGDbanvVI9aAyUCaLV4MvSv0BbKu9TZdSdGHrswYb+05J0x+r81Hha3bNkOW\n\t+wqoNAs/Z/068nJ1I7Cgo7I=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v6 6/6] vfio/pci: Add PCIe TPH SET_ST interface", "Date": "Wed, 6 May 2026 17:46:23 +0800", "Message-ID": "<20260506094623.29327-7-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260506094623.29327-1-fengchengwen@huawei.com>", "References": "<20260506094623.29327-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems500001.china.huawei.com (7.221.188.70) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Add VFIO_PCI_TPH_SET_ST operation to support batch programming of steering\ntag entries. If any entry fails, roll back successfully programmed entries\nto 0 to prevent inconsistent device state.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/vfio/pci/vfio_pci_core.c | 86 ++++++++++++++++++++++++++++++++\n 1 file changed, 86 insertions(+)", "diff": "diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex 45e641ab2a88..867d8694b56b 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1600,6 +1600,90 @@ static int vfio_pci_tph_get_st(struct vfio_pci_core_device *vdev,\n \treturn err;\n }\n \n+static int vfio_pci_tph_set_st(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct pci_dev *pdev = vdev->pdev;\n+\tstruct vfio_pci_tph_entry *ents;\n+\tstruct vfio_pci_tph_st st;\n+\tenum tph_mem_type mtype;\n+\tsize_t size, ents_off;\n+\tint i = 0, j, err;\n+\tu32 tab_loc;\n+\tu16 st_val;\n+\n+\ttab_loc = pcie_tph_get_st_table_loc(pdev);\n+\tif (tab_loc != PCI_TPH_LOC_CAP && tab_loc != PCI_TPH_LOC_MSIX)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (copy_from_user(&st, uarg, sizeof(st)))\n+\t\treturn -EFAULT;\n+\n+\tif (!st.count || st.count > VFIO_PCI_TPH_MAX_ENTRIES)\n+\t\treturn -EINVAL;\n+\n+\t/* Check reserved fields are zero */\n+\tif (memchr_inv(&st.reserved, 0, sizeof(st.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tsize = st.count * sizeof(*ents);\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, st) +\n+\t\t\tsizeof(struct vfio_pci_tph_st) + size)\n+\t\treturn -EINVAL;\n+\n+\tents = kvmalloc(size, GFP_KERNEL);\n+\tif (!ents)\n+\t\treturn -ENOMEM;\n+\n+\tents_off = offsetof(struct vfio_pci_tph_st, ents);\n+\tif (copy_from_user(ents, uarg + ents_off, size)) {\n+\t\terr = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (; i < st.count; i++) {\n+\t\t/* Check reserved fields are zero */\n+\t\tif (memchr_inv(&ents[i].reserved0, 0, sizeof(ents[i].reserved0)) ||\n+\t\t memchr_inv(&ents[i].reserved1, 0, sizeof(ents[i].reserved1))) {\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (ents[i].cpu == U32_MAX) {\n+\t\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, 0);\n+\t\t\tif (err)\n+\t\t\t\tgoto out;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_VM) {\n+\t\t\tmtype = TPH_MEM_TYPE_VM;\n+\t\t} else if (ents[i].mem_type == VFIO_PCI_TPH_MEM_TYPE_PM) {\n+\t\t\tmtype = TPH_MEM_TYPE_PM;\n+\t\t} else {\n+\t\t\terr = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\terr = pcie_tph_get_cpu_st(pdev, mtype, ents[i].cpu, &st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t\terr = pcie_tph_set_st_entry(pdev, ents[i].index, st_val);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t}\n+\n+out:\n+\tif (err) {\n+\t\t/* Roll back previously programmed entries to 0 */\n+\t\tfor (j = 0; j < i; j++)\n+\t\t\tpcie_tph_set_st_entry(pdev, ents[j].index, 0);\n+\t}\n+\tkvfree(ents);\n+\treturn err;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1618,6 +1702,8 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\treturn vfio_pci_tph_disable(vdev);\n \tcase VFIO_PCI_TPH_GET_ST:\n \t\treturn vfio_pci_tph_get_st(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_SET_ST:\n+\t\treturn vfio_pci_tph_set_st(vdev, &op, uarg + minsz);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n", "prefixes": [ "v6", "6/6" ] }