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GET /api/1.1/patches/2233349/?format=api
{ "id": 2233349, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2233349/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260506094623.29327-3-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260506094623.29327-3-fengchengwen@huawei.com>", "date": "2026-05-06T09:46:19", "name": "[v6,2/6] PCI/TPH: Export pcie_tph_get_st_modes() for external use", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ce1c3aef2aacea76aad49af54ba3ed987c71325e", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.1/people/92756/?format=api", "name": "fengchengwen", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260506094623.29327-3-fengchengwen@huawei.com/mbox/", "series": [ { "id": 502946, "url": "http://patchwork.ozlabs.org/api/1.1/series/502946/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502946", "date": "2026-05-06T09:46:19", "name": "vfio/pci: Add PCIe TPH support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/502946/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233349/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233349/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53841-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=Ez8h+2P4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-53841-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"Ez8h+2P4\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.223", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g9Vw01Yptz1y04\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 06 May 2026 19:49:20 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 6753F3022637\n\tfor <incoming@patchwork.ozlabs.org>; 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Wed, 6 May 2026 17:46:30 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778060796; cv=none;\n b=V/JtFERem8hekCe70w+JNEeBpXn9AVJKCCom+lA3wuA+HqSkZDdgdfxKNLSpsTtR/QRtncVwwT4MqaWWHxrPeV53hvHXwraHb232YWA5X8OuGbkl8dO3El0Sce/6E1gBuLQaRW29G2r4UdcigtRSpEmPXPyjq7Kf6gz40CaMrPo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778060796; c=relaxed/simple;\n\tbh=nc+kMNBiVpPpNZkDNxsYRsFUiQTmFjOejAYkxZ+729E=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=sv8yi1gE4F3k5zwc77azyVpRzYojDL+D51/e4wRJxalz1hDzJcCYkLcqbwB2r0uNGOao+nVDCPOXt+kA4KL90sQbbwOeQhGkTDqBghN3aH6yHYA9zDZH3JnC6zXyHWpQ11zN91ICZD7fkhYeyjxhwcrwr8H31DGACKTcbO9y6NQ=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=Ez8h+2P4; arc=none smtp.client-ip=113.46.200.223", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=Ehw2qEU2k6FkgAstiAZCoKUA1h6nFfq+GSfhBIOtQO8=;\n\tb=Ez8h+2P4NukROIwAsoPu2o3OSPv4tJIon7d+jZQWNits3e2jxuchEKMx+Y0Zdd0WcAUpftSxr\n\ti5+vBKqyQYIn/xrfgZhs7Na70j+1bRt9xiCUEImFggmQgJ+XVraCl5uivmVhjHL3fK6hswDBU0q\n\tCZ68bpzkRx2Io7z7zW7Lcek=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <helgaas@kernel.org>, <wei.huang2@amd.com>,\n\t<wangzhou1@hisilicon.com>, <wangyushan12@huawei.com>,\n\t<liuyonglong@huawei.com>, <kvm@vger.kernel.org>, <linux-pci@vger.kernel.org>", "Subject": "[PATCH v6 2/6] PCI/TPH: Export pcie_tph_get_st_modes() for external\n use", "Date": "Wed, 6 May 2026 17:46:19 +0800", "Message-ID": "<20260506094623.29327-3-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260506094623.29327-1-fengchengwen@huawei.com>", "References": "<20260506094623.29327-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems500001.china.huawei.com (7.221.188.70) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Export the helper to retrieve supported PCIe TPH steering tag modes so\nthat drivers like VFIO can query and expose device capabilities to\nuserspace.\n\nAdd stub functions for pcie_tph_get_st_table_size() and\npcie_tph_get_st_table_loc() when !CONFIG_PCI_TPH.\n\nAdd tph_cap validation for pcie_tph_get_st_modes() and\npcie_tph_get_st_table_loc() to prevent invalid PCI configuration\nspace access when TPH is not supported.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nAcked-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/tph.c | 20 ++++++++++++++++++--\n include/linux/pci-tph.h | 7 +++++++\n 2 files changed, 25 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex f17b74b5fb1e..ba31b010f67a 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -145,15 +145,27 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type)\n \tpci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);\n }\n \n-static u8 get_st_modes(struct pci_dev *pdev)\n+/**\n+ * pcie_tph_get_st_modes - Get supported Steering Tag modes\n+ * @pdev: PCI device to query\n+ *\n+ * Return:\n+ * Bitmask of supported ST modes (PCI_TPH_CAP_ST_NS, PCI_TPH_CAP_ST_IV,\n+ * PCI_TPH_CAP_ST_DS)\n+ */\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n+\tif (!pdev->tph_cap)\n+\t\treturn 0;\n+\n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n \treg &= PCI_TPH_CAP_ST_NS | PCI_TPH_CAP_ST_IV | PCI_TPH_CAP_ST_DS;\n \n \treturn reg;\n }\n+EXPORT_SYMBOL(pcie_tph_get_st_modes);\n \n /**\n * pcie_tph_get_st_table_loc - Return the device's ST table location\n@@ -168,6 +180,9 @@ u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n+\tif (!pdev->tph_cap)\n+\t\treturn PCI_TPH_LOC_NONE;\n+\n \tpci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®);\n \n \treturn reg & PCI_TPH_CAP_LOC_MASK;\n@@ -183,6 +198,7 @@ u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n \tu32 reg;\n \tu32 loc;\n \n+\t/* Check ST table location first */\n \tloc = pcie_tph_get_st_table_loc(pdev);\n \tif (loc != PCI_TPH_LOC_CAP)\n \t\treturn 0;\n@@ -394,7 +410,7 @@ int pcie_enable_tph(struct pci_dev *pdev, int mode)\n \n \t/* Sanitize and check ST mode compatibility */\n \tmode &= PCI_TPH_CTRL_MODE_SEL_MASK;\n-\tdev_modes = get_st_modes(pdev);\n+\tdev_modes = pcie_tph_get_st_modes(pdev);\n \tif (!((1 << mode) & dev_modes))\n \t\treturn -EINVAL;\n \ndiff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h\nindex be68cd17f2f8..586c75b19e01 100644\n--- a/include/linux/pci-tph.h\n+++ b/include/linux/pci-tph.h\n@@ -30,6 +30,7 @@ void pcie_disable_tph(struct pci_dev *pdev);\n int pcie_enable_tph(struct pci_dev *pdev, int mode);\n u16 pcie_tph_get_st_table_size(struct pci_dev *pdev);\n u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev);\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev);\n #else\n static inline int pcie_tph_set_st_entry(struct pci_dev *pdev,\n \t\t\t\t\tunsigned int index, u16 tag)\n@@ -41,6 +42,12 @@ static inline int pcie_tph_get_cpu_st(struct pci_dev *dev,\n static inline void pcie_disable_tph(struct pci_dev *pdev) { }\n static inline int pcie_enable_tph(struct pci_dev *pdev, int mode)\n { return -EINVAL; }\n+static inline u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n+{ return 0; }\n+static inline u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n+{ return 0x7FF; /* Values that do not appear in normal case */ }\n+static inline u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n+{ return 0; }\n #endif\n \n #endif /* LINUX_PCI_TPH_H */\n", "prefixes": [ "v6", "2/6" ] }