Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2232535/?format=api
{ "id": 2232535, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232535/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260504171342.1655882-1-raymondmaoca@gmail.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/1.1/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504171342.1655882-1-raymondmaoca@gmail.com>", "date": "2026-05-04T17:13:40", "name": "[v2,1/3] lib: utils: irqchip: implement APLIC hwirq operation hooks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c8206fb49e3057a101e446103be6460911da02bc", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/1.1/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260504171342.1655882-1-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 502701, "url": "http://patchwork.ozlabs.org/api/1.1/series/502701/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=502701", "date": "2026-05-04T17:13:40", "name": "[v2,1/3] lib: utils: irqchip: implement APLIC hwirq operation hooks", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502701/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232535/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232535/checks/", "tags": {}, "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=w/3ydSO5;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=qxKlV2NI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g8Ssz0bqXz1yJ9\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 05 May 2026 03:13:59 +1000 (AEST)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wJwrk-0000000Do0Q-0zkr;\n\tMon, 04 May 2026 17:13:56 +0000", "from mail-qt1-x82b.google.com ([2607:f8b0:4864:20::82b])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wJwrh-0000000Dnzy-1OQG\n\tfor opensbi@lists.infradead.org;\n\tMon, 04 May 2026 17:13:54 +0000", "by mail-qt1-x82b.google.com with SMTP id\n d75a77b69052e-50e63771d91so46844341cf.0\n for <opensbi@lists.infradead.org>;\n Mon, 04 May 2026 10:13:52 -0700 (PDT)", "from ubuntu.localdomain (172-97-209-197.cpe.distributel.net.\n [172.97.209.197])\n by smtp.gmail.com with ESMTPSA id\n d75a77b69052e-51040927789sm102332871cf.11.2026.05.04.10.13.50\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 04 May 2026 10:13:50 -0700 (PDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc\n\t:To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=WlZ7mvN5CwiLpd9daFhgQyaqtCo6vw00i4zUuxuA7ng=; b=w/3ydSO5uai9rA\n\twTJDVyr0N1KLtRAwgXN76sOduoHS8MRw3dZsJ3ylZYbQN5kDtzsJMlPFbN5BNxsv2ZxyyISD2A7yF\n\thWIpCdrKRFp7XNhzNxgHePh8YZPT5SuVDPSeNMETmje9mt57QN2+9eW2ifY3bLz/3zOkDxwUYJVqV\n\tDEGqTbsrxYp+VXNyidfZ/Ix6jDyX1osGFTZl5xiFWSWD9JTArN01agjditYb3khYZlbeF9o+cjw/w\n\tVhFKoxYACcxLqasgoL+GVBSUjwsa/nSw1ouiYhNUARKrwRFfn8tYqvFNLdpxLqydnivyhGkFSYHhq\n\t+bCPf9m6vkDUGLX+QCqw==;", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777914831; x=1778519631;\n darn=lists.infradead.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=cwcU9C+Fb00TAYZBFd/cllroMLG99hVE1xsW6E2kDDg=;\n b=qxKlV2NIw4Q3gAGrVD5vzfzYP3BxM5fitcL0NgbuLTlGIFUoCJX+0lpcajshz0VyqE\n Dr+VpDMVnUwfi3T6B1JGZhtlW3Ce/d2nMm7apnOAWGSXMRZ1APVd0P1uu0e+kSeAy2Ya\n rtWAlaG60A9suvtaveBLXxQAucPj6ZHPQGUB4XdlTyTiuQjMK568EgSJVAc9gRCdFFuj\n 2oGZR9t5jOHi2zXLJIjROJ/uQnS5gcVcRaFcyvu9ggST3sJ8iIvNHAU7WEO/SA6GylVu\n aVItTpkP2zzvDFnYiEyfm79xlSc8kW/DLdb2xPw9PwXIFqR2fONQ7n7eAfQG3Zwvpwog\n WAVA==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777914831; x=1778519631;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=cwcU9C+Fb00TAYZBFd/cllroMLG99hVE1xsW6E2kDDg=;\n b=hK72v6nWkJG7NhtW3aUrkhZ9jGgxsCZx39V2qz5oBYiznhyp6eraWLkV5b6JB1prXs\n tYU9SjeCBiq9phugsAobmVarEO1DE5WlZz1d9T++GPIIncOWoG9sdwM5FPoYnYWYGQVd\n kp/f1vkAqoWyLMbW6DNeNZMIgWtDsGLAg3YslzzR+XtFKwT8tbEcdgNNqgfxDbN70cxw\n 23ozyRkyZjBQroWzOYOXMUQua6sWfPVfNW5DdxullrauQ4aLepZ4Rh9X2eYkdyDGlZDY\n XLi3DYiziOGK/TaF60Fv4btSWLt/pWi/6Rqk/4uOYuaixtI/g83EHYQAB1+hyob/RBqA\n p6ew==", "X-Gm-Message-State": "AOJu0Yx+ijNlCFWptu+EVFMdQ14fSuQXQuWwrsMn3+IxWZZfywobcyLK\n\tpo651EGtZ5LkPDdjFids34r4SFoMmruF+e9u09zoTOVfRgty0oYHEc9YPn+dghlns6Q=", "X-Gm-Gg": "AeBDieutrO8o1TIvpJcbGik6EtBPbrwOIYzeurU3zuje1DvmY/FOz2VH5nTvrHYvUA/\n\toZhLlvvasZMmneflyVvqfz+VrCEux1sniPmQrPQ/hTm8SevihZmI1fEgpUUCka5lPTZ8xCxkg1e\n\tib1kRejbxxR3yOOYtvRL7yuN7rr7MRBptc9V4a314+BqqRXbqkQ3JkzLIhFPzdA9wzgtADoZEHW\n\tMzTqFjfJWcFE6niBoRgAuGJp2BeMnzpg63yYP2vbQh99dRy/2WenJCfbMOrQU7Fh5K6sbyhnXhD\n\tRe1XIlcUjzfDhALzoX+mZ9F7F7RWUbVvV40eIp5OyLswcNhYYtIMvkdUqZXWEmmm3uxZ4sNqiTK\n\tO4EPd7KVXAwg9vEHLs55xlKGXYm/ZdofI4LLncUfDrDp4MmCcDXlVEOH8dQCNXyTilHTJS59kOI\n\tOkIMTEYGmWmRpNd6auPXyLJyfdhBTWdPIiesXM3lPIEqMeUIB1NGLyz9Xy1qa78rmswynbJlCkp\n\ttzn3D3vJuHW4taFRX24DQ==", "X-Received": "by 2002:a05:622a:5485:b0:50f:be4f:465e with SMTP id\n d75a77b69052e-5104c014372mr156166051cf.53.1777914831203;\n Mon, 04 May 2026 10:13:51 -0700 (PDT)", "From": "Raymond Mao <raymondmaoca@gmail.com>", "To": "opensbi@lists.infradead.org", "Cc": "scott@riscstar.com,\n\tdave.patel@riscstar.com,\n\traymond.mao@riscstar.com,\n\trobin.randhawa@sifive.com,\n\tsamuel.holland@sifive.com,\n\tanup.patel@qti.qualcomm.com,\n\tanuppate@qti.qualcomm.com,\n\tanup@brainfault.org,\n\tdhaval@rivosinc.com,\n\tpeter.lin@sifive.com", "Subject": "[PATCH v2 1/3] lib: utils: irqchip: implement APLIC hwirq operation\n hooks", "Date": "Mon, 4 May 2026 13:13:40 -0400", "Message-Id": "<20260504171342.1655882-1-raymondmaoca@gmail.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260504_101353_393945_D0841C60 ", "X-CRM114-Status": "GOOD ( 19.46 )", "X-Spam-Score": "-2.1 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Raymond Mao Implement the APLIC hardware interrupt\n hooks\n used by the generic irqchip framework for M-mode direct-mode wired\n interrupts.\n Program a minimal APLIC direct-mode configuration during hwirq setup and\n claim external interrupts via IDC.CLAIMI. Add the helper logic needed to\n derive\n the source ID from CLAIMI, map hart index to ID [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:82b listed in]\n [list.dnswl.org]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n provider\n [raymondmaoca(at)gmail.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Raymond Mao <raymond.mao@riscstar.com>\n\nImplement the APLIC hardware interrupt hooks used by the generic\nirqchip framework for M-mode direct-mode wired interrupts.\n\nProgram a minimal APLIC direct-mode configuration during hwirq setup\nand claim external interrupts via IDC.CLAIMI. Add the helper logic\nneeded to derive the source ID from CLAIMI, map hart index to IDC\nindex, skip delegated interrupts, and register process_hwirqs()\nonly for the M-mode direct-mode provider.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\n---\n lib/utils/irqchip/aplic.c | 227 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 227 insertions(+)", "diff": "diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c\nindex ec69c82b..3f4991b5 100644\n--- a/lib/utils/irqchip/aplic.c\n+++ b/lib/utils/irqchip/aplic.c\n@@ -245,6 +245,220 @@ static int aplic_check_msicfg(struct aplic_msicfg_data *msicfg)\n \treturn 0;\n }\n \n+static inline void *aplic_idc_base(unsigned long aplic_addr, u32 idc_index)\n+{\n+\treturn (void *)(aplic_addr + APLIC_IDC_BASE +\n+\t\t\t(unsigned long)idc_index * APLIC_IDC_SIZE);\n+}\n+\n+static inline struct aplic_data *aplic_irqchip_to_data(struct sbi_irqchip_device *chip)\n+{\n+\treturn container_of(chip, struct aplic_data, irqchip);\n+}\n+\n+static bool aplic_hwirq_delegated(const struct aplic_data *aplic, u32 hwirq)\n+{\n+\tu32 i;\n+\n+\tfor (i = 0; i < APLIC_MAX_DELEGATE; i++) {\n+\t\tconst struct aplic_delegate_data *deleg = &aplic->delegate[i];\n+\n+\t\tif (!deleg->first_irq || !deleg->last_irq)\n+\t\t\tcontinue;\n+\t\tif (deleg->first_irq <= hwirq && hwirq <= deleg->last_irq)\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+static bool aplic_mmode_direct(const struct aplic_data *aplic)\n+{\n+\treturn aplic->targets_mmode && aplic->num_idc;\n+}\n+\n+static int aplic_hartindex_to_idc_index(const struct aplic_data *aplic,\n+\t\t\t\t\tu32 hartindex)\n+{\n+\tu32 i;\n+\n+\tif (!aplic->num_idc)\n+\t\treturn SBI_ENODEV;\n+\n+\tif (aplic->idc_map) {\n+\t\tfor (i = 0; i < aplic->num_idc; i++) {\n+\t\t\tif (aplic->idc_map[i] == hartindex)\n+\t\t\t\treturn i;\n+\t\t}\n+\n+\t\treturn SBI_ENODEV;\n+\t}\n+\n+\tif (hartindex < aplic->num_idc)\n+\t\treturn hartindex;\n+\n+\treturn SBI_ENODEV;\n+}\n+\n+static int aplic_hwirq_target_idc_index(struct sbi_irqchip_device *chip)\n+{\n+\tu32 hartindex = current_hartindex();\n+\n+\tif (!sbi_hartmask_test_hartindex(hartindex, &chip->target_harts)) {\n+\t\tsbi_hartmask_for_each_hartindex(hartindex, &chip->target_harts)\n+\t\t\tbreak;\n+\t\tif (hartindex >= SBI_HARTMASK_MAX_BITS)\n+\t\t\treturn SBI_ENODEV;\n+\t}\n+\n+\treturn aplic_hartindex_to_idc_index(aplic_irqchip_to_data(chip),\n+\t\t\t\t\t hartindex);\n+}\n+\n+static u32 aplic_domaincfg_value(void)\n+{\n+\tu32 val = APLIC_DOMAINCFG_IE;\n+\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\tval |= APLIC_DOMAINCFG_BE;\n+#endif\n+\n+\treturn val;\n+}\n+\n+static void aplic_hwirq_mask(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *aplic = aplic_irqchip_to_data(chip);\n+\n+\tif (!hwirq || aplic_hwirq_delegated(aplic, hwirq))\n+\t\treturn;\n+\n+\tif (!aplic->addr || hwirq > aplic->num_source)\n+\t\treturn;\n+\n+\t/* Disable source */\n+\twritel(hwirq, (void *)(aplic->addr + APLIC_CLRIENUM));\n+}\n+\n+static void aplic_hwirq_unmask(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *aplic = aplic_irqchip_to_data(chip);\n+\n+\tif (!hwirq || aplic_hwirq_delegated(aplic, hwirq))\n+\t\treturn;\n+\n+\tif (!aplic->addr || hwirq > aplic->num_source)\n+\t\treturn;\n+\n+\t/* Enable source */\n+\twritel(hwirq, (void *)(aplic->addr + APLIC_SETIENUM));\n+}\n+\n+static int aplic_hwirq_claim(struct sbi_irqchip_device *chip, u32 *hwirq)\n+{\n+\tstruct aplic_data *aplic = aplic_irqchip_to_data(chip);\n+\tint idc_index;\n+\tvoid *idc;\n+\tu32 v, id;\n+\n+\tif (!hwirq)\n+\t\treturn SBI_EINVAL;\n+\n+\tidc_index = aplic_hartindex_to_idc_index(aplic, current_hartindex());\n+\tif (!aplic->addr || idc_index < 0)\n+\t\treturn SBI_ENODEV;\n+\n+\tidc = aplic_idc_base(aplic->addr, idc_index);\n+\n+\t/*\n+\t * Read CLAIMI: returns TOPI value.\n+\t * ID==0 means spurious interrupt (spec-defined).\n+\t */\n+\tv = readl(idc + APLIC_IDC_CLAIMI); /* dequeue */\n+\n+\tid = (v >> APLIC_IDC_TOPI_ID_SHIFT) & APLIC_IDC_TOPI_ID_MASK;\n+\n+\t/* ID==0 means spurious / no pending wired interrupt */\n+\tif (!id)\n+\t\treturn SBI_ENOENT;\n+\n+\t/* Bound check against DT-discovered num_src */\n+\tif (id > aplic->num_source)\n+\t\treturn SBI_EINVAL;\n+\n+\t*hwirq = id;\n+\n+\treturn SBI_OK;\n+}\n+\n+static int aplic_hwirq_setup(struct sbi_irqchip_device *chip, u32 hwirq)\n+{\n+\tstruct aplic_data *aplic = aplic_irqchip_to_data(chip);\n+\tunsigned long idc;\n+\tint idc_index;\n+\n+\tif (!hwirq || hwirq > aplic->num_source)\n+\t\treturn SBI_EINVAL;\n+\tif (!aplic_mmode_direct(aplic))\n+\t\treturn SBI_ENOTSUPP;\n+\tif (aplic_hwirq_delegated(aplic, hwirq))\n+\t\treturn SBI_ENOTSUPP;\n+\n+\tidc_index = aplic_hwirq_target_idc_index(chip);\n+\tif (idc_index < 0)\n+\t\treturn idc_index;\n+\n+\tidc = aplic->addr + APLIC_IDC_BASE + idc_index * APLIC_IDC_SIZE;\n+\n+\t/* APLIC: sourcecfg/target/enable */\n+\twritel(APLIC_SOURCECFG_SM_LEVEL_HIGH,\n+\t (void *)(aplic->addr + APLIC_SOURCECFG_BASE + (hwirq - 1) * 4));\n+\n+\twritel(((u32)idc_index << APLIC_TARGET_HART_IDX_SHIFT) |\n+\t APLIC_DEFAULT_PRIORITY,\n+\t (void *)(aplic->addr + APLIC_TARGET_BASE + (hwirq - 1) * 4));\n+\n+\twritel(hwirq, (void *)(aplic->addr + APLIC_SETIENUM));\n+\n+\t/* Direct mode for aia=aplic: DM=0 => don't set DM bit */\n+\twritel(aplic_domaincfg_value(), (void *)(aplic->addr + APLIC_DOMAINCFG));\n+\n+\t/* IDC delivery */\n+\twritel(APLIC_ENABLE_IDELIVERY, (void *)(idc + APLIC_IDC_IDELIVERY));\n+\twritel(APLIC_ENABLE_ITHRESHOLD, (void *)(idc + APLIC_IDC_ITHRESHOLD));\n+\n+\treturn SBI_OK;\n+}\n+\n+static int aplic_process_hwirqs(struct sbi_irqchip_device *chip)\n+{\n+\tif (!chip)\n+\t\treturn SBI_ENODEV;\n+\n+\tfor (;;) {\n+\t\tu32 hwirq = 0;\n+\t\tint rc = aplic_hwirq_claim(chip, &hwirq);\n+\n+\t\tif (rc == SBI_ENOENT)\n+\t\t\tbreak;\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tif (!hwirq)\n+\t\t\tbreak;\n+\n+\t\tif (hwirq > chip->num_hwirq) {\n+\t\t\treturn SBI_EINVAL;\n+\t\t}\n+\n+\t\trc = sbi_irqchip_process_hwirq(chip, hwirq);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\treturn SBI_OK;\n+}\n+\n int aplic_cold_irqchip_init(struct aplic_data *aplic)\n {\n \tint rc;\n@@ -308,6 +522,19 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)\n \t/* Register irqchip device */\n \taplic->irqchip.id = aplic->unique_id;\n \taplic->irqchip.num_hwirq = aplic->num_source + 1;\n+\taplic->irqchip.hwirq_mask = aplic_hwirq_mask;\n+\taplic->irqchip.hwirq_unmask = aplic_hwirq_unmask;\n+\t/*\n+\t * Only the domain that directly injects interrupts into M-mode external\n+\t * interrupt line should provide process_hwirqs().\n+\t *\n+\t * The other domain (e.g. S-mode) may still be registered so that its\n+\t * other ops (mask/unmask/config/etc.) can be used, but it must not\n+\t * claim to be the external interrupt line provider.\n+\t */\n+\tif (aplic_mmode_direct(aplic))\n+\t\taplic->irqchip.process_hwirqs = aplic_process_hwirqs;\n+\taplic->irqchip.hwirq_setup = aplic_hwirq_setup;\n \trc = sbi_irqchip_add_device(&aplic->irqchip);\n \tif (rc)\n \t\treturn rc;\n", "prefixes": [ "v2", "1/3" ] }