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GET /api/1.1/patches/2232514/?format=api
{ "id": 2232514, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-6-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-6-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:39", "name": "[v5,06/15] target/arm: add MTX to MTEDESC and DisasContext", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0f21c09f84b318e52debb274873a23fa4a5b7218", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-6-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232514/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232514/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=RIGxRlmp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-6-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=6070;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=pus4GwsaxCbMuSf6IijKDSfjMEIqDUvfVkkjkvUKGzg=;\n b=QlIVqFyFW8q1abqB3HOKPtlOYkl5QLhR3+gmHWNlhUj+6CaFF1DYWHOS46SkMwNFKmrSShP1t\n 7nTmuFiNkhRDFFmaH1HiY8YCqncRscp+pOUy1Y/hw+X+wojbArk7txT", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::831;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x831.google.com", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1,\n FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add fields for MTX to DisasContext and MTEDESC. With MTE4, the fields\nwill be needed in future patches that alter tag check, tag load and tag\nstore behavior.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.h | 1 +\n target/arm/tcg/hflags.c | 4 ++++\n target/arm/tcg/translate-a64.c | 7 +++++++\n target/arm/tcg/translate.h | 1 +\n 5 files changed, 18 insertions(+)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 4d130b4b2b..90d4ed37c2 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1159,6 +1159,11 @@ static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1;\n }\n \n+static inline bool isar_feature_aa64_mte_mtx(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTEX) != 0;\n+}\n+\n static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 706ade5784..6e2b70dae5 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -2529,6 +2529,7 @@ FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1)\n FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2)\n FIELD(TBFLAG_A64, MTE_STORE_ONLY, 45, 1)\n FIELD(TBFLAG_A64, MTE0_STORE_ONLY, 46, 1)\n+FIELD(TBFLAG_A64, MTX, 47, 2)\n \n /*\n * Helpers for using the above. Note that only the A64 accessors use\ndiff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c\nindex e753124c4c..40a934a8af 100644\n--- a/target/arm/tcg/hflags.c\n+++ b/target/arm/tcg/hflags.c\n@@ -460,6 +460,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n }\n /* Cache TCMA as well as TBI. */\n DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));\n+ /* Cache MTX. */\n+ if (cpu_isar_feature(aa64_mte_mtx, env_archcpu(env))) {\n+ DP_TBFLAG_A64(flags, MTX, mtx);\n+ }\n }\n \n if (cpu_isar_feature(aa64_gcs, env_archcpu(env))) {\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex ce6249649a..cd86178d56 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -312,6 +312,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,\n desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);\n desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);\n desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(memop));\n+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);\n desc = FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1);\n \n ret = tcg_temp_new_i64();\n@@ -345,6 +346,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,\n desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);\n desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);\n desc = FIELD_DP32(desc, MTEDESC, ALIGN, memop_alignment_bits(single_mop));\n+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);\n desc = FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1);\n \n ret = tcg_temp_new_i64();\n@@ -3003,6 +3005,7 @@ static void handle_sys(DisasContext *s, bool isread,\n desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));\n desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);\n desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);\n+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);\n \n tcg_rt = tcg_temp_new_i64();\n gen_helper_mte_check_zva(tcg_rt, tcg_env,\n@@ -4873,6 +4876,7 @@ static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue,\n desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);\n desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);\n desc = FIELD_DP32(desc, MTEDESC, WRITE, true);\n+ desc = FIELD_DP32(desc, MTEDESC, MTX, s->mtx);\n /* SIZEM1 and ALIGN we leave 0 (byte write) */\n }\n /* The helper function always needs the memidx even with MTE disabled */\n@@ -4927,11 +4931,13 @@ static bool do_CPY(DisasContext *s, arg_cpy *a, bool is_epilogue, CpyFn fn)\n if (s->mte_active[runpriv]) {\n rdesc = FIELD_DP32(rdesc, MTEDESC, TBI, s->tbid);\n rdesc = FIELD_DP32(rdesc, MTEDESC, TCMA, s->tcma);\n+ rdesc = FIELD_DP32(rdesc, MTEDESC, MTX, s->mtx);\n }\n if (s->mte_active[wunpriv]) {\n wdesc = FIELD_DP32(wdesc, MTEDESC, TBI, s->tbid);\n wdesc = FIELD_DP32(wdesc, MTEDESC, TCMA, s->tcma);\n wdesc = FIELD_DP32(wdesc, MTEDESC, WRITE, true);\n+ wdesc = FIELD_DP32(wdesc, MTEDESC, MTX, s->mtx);\n }\n /* The helper function needs these parts of the descriptor regardless */\n rdesc = FIELD_DP32(rdesc, MTEDESC, MIDX, rmemidx);\n@@ -10701,6 +10707,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);\n dc->mte_store_only[0] = EX_TBFLAG_A64(tb_flags, MTE_STORE_ONLY);\n dc->mte_store_only[1] = EX_TBFLAG_A64(tb_flags, MTE0_STORE_ONLY);\n+ dc->mtx = EX_TBFLAG_A64(tb_flags, MTX);\n dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);\n dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);\n dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex c74a4f6675..75d1b0fbd9 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -82,6 +82,7 @@ typedef struct DisasContext {\n uint8_t tbii; /* TBI1|TBI0 for insns */\n uint8_t tbid; /* TBI1|TBI0 for data */\n uint8_t tcma; /* TCMA1|TCMA0 for MTE */\n+ uint8_t mtx; /* MTX1|MTX0 for MTE */\n bool ns; /* Use non-secure CPREG bank on access */\n int fp_excp_el; /* FP exception EL or 0 if enabled */\n int sve_excp_el; /* SVE exception EL or 0 if enabled */\n", "prefixes": [ "v5", "06/15" ] }