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GET /api/1.1/patches/2232507/?format=api
{ "id": 2232507, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-1-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-1-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:34", "name": "[v5,01/15] target/arm: implement MTE_PERM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6ffab03e73ea7308de94f9d1b637eddd5d4e2c72", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-1-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232507/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232507/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=LR72MCY1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-1-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=4690;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=o+Y1Qx7rXo8nqYOsXdVp4KZ2JR8/3aepK/F4Yuu4kE0=;\n b=zShtqvYHaHGxVUpXOT9hN97Pcb+j1GeiUbhhEHsaC676k/VLLvNJIcBHb1PynGBkOxRWoCDSM\n mDZxzJq04lgDnWgZNUQoLQ8X07LzdpulYY8IeFv3KpEvVjTiZ1Kiowd", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::82d;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x82d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduces a new stage 2 memory attribute, NoTagAccess, that raises a\nstage 2 data abort on a tag check, tag read, or tag write.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/ptw.c | 25 ++++++++++++++++++++++---\n target/arm/tcg/mte_helper.c | 38 ++++++++++++++++++++++++++++++++++++--\n 3 files changed, 63 insertions(+), 5 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 6e5212ff6c..c1f2336055 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1149,6 +1149,11 @@ static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3;\n }\n \n+static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1;\n+}\n+\n static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;\ndiff --git a/target/arm/ptw.c b/target/arm/ptw.c\nindex 7b993bb5b3..4fdb27697d 100644\n--- a/target/arm/ptw.c\n+++ b/target/arm/ptw.c\n@@ -3394,7 +3394,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,\n ARMCacheAttrs s1, ARMCacheAttrs s2)\n {\n ARMCacheAttrs ret;\n- bool tagged = false;\n+ bool tagged, notagaccess = false;\n \n assert(!s1.is_s2_format);\n ret.is_s2_format = false;\n@@ -3404,6 +3404,18 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,\n s1.attrs = 0xff;\n }\n \n+ if (hcr & HCR_FWB) {\n+ if (s2.attrs >= 0xe) {\n+ notagaccess = true;\n+ s2.attrs = 0x7;\n+ }\n+ } else {\n+ if (s2.attrs == 0x4) {\n+ notagaccess = true;\n+ s2.attrs = 0xf;\n+ }\n+ }\n+\n /* Combine shareability attributes (table D4-43) */\n if (s1.shareability == 2 || s2.shareability == 2) {\n /* if either are outer-shareable, the result is outer-shareable */\n@@ -3435,9 +3447,16 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,\n ret.shareability = 2;\n }\n \n- /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */\n+ /*\n+ * The attr encoding 0xe0 corresponds to Tagged NoTagAccess and is only\n+ * valid with FEAT_MTE_PERM (otherwise RESERVED, constrained\n+ * unpredictable)). The presence of this feature is checked in\n+ * allocation_tag_mem_probe, where Tagged NoTagAccess has its effect. See\n+ * J1.3.5.2 EncodePARAttrs.\n+ * TODO: CombineS1S2Desc does not consider transient, only WB, RWA.\n+ */\n if (tagged && ret.attrs == 0xff) {\n- ret.attrs = 0xf0;\n+ ret.attrs = notagaccess ? 0xe0 : 0xf0;\n }\n \n return ret;\ndiff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c\nindex a9fb979f63..bf35dc10ce 100644\n--- a/target/arm/tcg/mte_helper.c\n+++ b/target/arm/tcg/mte_helper.c\n@@ -58,6 +58,27 @@ static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)\n return tag;\n }\n \n+#ifndef CONFIG_USER_ONLY\n+/*\n+ * Constructs S2 Permission Fault as described in ARM ARM \"Stage 2 Memory\n+ * Tagging Attributes\".\n+ */\n+static void mte_perm_check_fail(CPUARMState *env, uint64_t dirty_ptr,\n+ uintptr_t ra, bool is_write)\n+{\n+ uint64_t syn;\n+\n+ env->exception.vaddress = dirty_ptr;\n+\n+ syn = syn_data_abort_no_iss(0, 0, 0, 0, 0, is_write, 0);\n+\n+ syn |= BIT_ULL(41); /* TagAccess is bit 41 */\n+\n+ raise_exception_ra(env, EXCP_DATA_ABORT, syn, 2, ra);\n+ g_assert_not_reached();\n+}\n+#endif\n+\n uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx,\n uint64_t ptr, MMUAccessType ptr_access,\n int ptr_size, MMUAccessType tag_access,\n@@ -117,8 +138,21 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx,\n }\n assert(!(flags & TLB_INVALID_MASK));\n \n- /* If the virtual page MemAttr != Tagged, access unchecked. */\n- if (full->extra.arm.pte_attrs != 0xf0) {\n+ switch (full->extra.arm.pte_attrs) {\n+ case 0xf0: /* Tagged */\n+ break;\n+\n+ case 0xe0: /* NoTagAccess */\n+ if (cpu_isar_feature(aa64_mteperm, env_archcpu(env))) {\n+ if (probe) {\n+ return NULL;\n+ }\n+ assert(ra);\n+ mte_perm_check_fail(env, ptr, ra, tag_access == MMU_DATA_STORE);\n+ }\n+ /* fall through */\n+\n+ default: /* Not Tagged */\n return NULL;\n }\n \n", "prefixes": [ "v5", "01/15" ] }