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GET /api/1.1/patches/2232506/?format=api
{ "id": 2232506, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232506/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-10-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-10-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:43", "name": "[v5,10/15] target/arm: fault on tag store to canonical tag", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6528bad99c09217e33e37984a88f398d8e8635ee", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-10-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232506/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232506/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 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d75a77b69052e-5104bf7adbemr152565081cf.36.1777909883302;\n Mon, 04 May 2026 08:51:23 -0700 (PDT)", "From": "Gabriel Brookman <brookmangabriel@gmail.com>", "Date": "Mon, 04 May 2026 11:50:43 -0400", "Subject": "[PATCH v5 10/15] target/arm: fault on tag store to canonical tag", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-10-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=11299;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=aYIMM7VEzYa/cnI4zU8L0nd+u7JcOWA7N9KPcn8AdK4=;\n b=lLShDTqRAufOQmsE/EniKdWTjbF9bkdym1vepOMsiqR0sLekNNJfHQcrm8MtEI7tRMhgPN4T7\n Rwxx24qISGfDkBvfZ6O+qg+Zn5oJXQYSk7w0gABM//wKLMJvv56zxk9", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::82b;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x82b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "According to ARM ARM, section \"Memory region tagging types\", tag-store\ninstructions targeting canonically tagged regions cause a stage 1\npermission fault with MTX enabled.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\n---\n target/arm/tcg/helper-a64-defs.h | 12 ++++-----\n target/arm/tcg/mte_helper.c | 57 +++++++++++++++++++++++++++++++---------\n target/arm/tcg/translate-a64.c | 26 +++++++++++-------\n 3 files changed, 67 insertions(+), 28 deletions(-)", "diff": "diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex c08c8c3991..136d246a68 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -103,15 +103,15 @@ DEF_HELPER_FLAGS_3(mte_check_zva, TCG_CALL_NO_WG, i64, env, i32, i64)\n DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)\n DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32)\n DEF_HELPER_FLAGS_4(ldg, TCG_CALL_NO_WG, i64, env, i64, i64, i32)\n-DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64)\n-DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64)\n+DEF_HELPER_FLAGS_4(stg, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n+DEF_HELPER_FLAGS_4(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64)\n-DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64)\n-DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64)\n+DEF_HELPER_FLAGS_4(st2g, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n+DEF_HELPER_FLAGS_4(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64)\n DEF_HELPER_FLAGS_3(ldgm, TCG_CALL_NO_WG, i64, env, i64, i32)\n-DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64)\n-DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64)\n+DEF_HELPER_FLAGS_4(stgm, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n+DEF_HELPER_FLAGS_4(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64, i32)\n \n DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG,\n noreturn, env, i64, i32, i32)\ndiff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c\nindex 8ed31ca2d8..ad5cdd558e 100644\n--- a/target/arm/tcg/mte_helper.c\n+++ b/target/arm/tcg/mte_helper.c\n@@ -231,6 +231,20 @@ uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx,\n #endif\n }\n \n+static void canonical_tag_write_fail(CPUARMState *env,\n+ uint64_t dirty_ptr, uintptr_t ra)\n+{\n+ uint64_t syn;\n+\n+ env->exception.vaddress = dirty_ptr;\n+\n+ syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, 1, 0);\n+ syn |= BIT_ULL(42); /* TnD is bit 42 */\n+\n+ raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra);\n+ g_assert_not_reached();\n+}\n+\n static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,\n uint64_t ptr, MMUAccessType ptr_access,\n int ptr_size, MMUAccessType tag_access,\n@@ -362,7 +376,7 @@ static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag)\n typedef void stg_store1(uint64_t, uint8_t *, int);\n \n static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,\n- uintptr_t ra, stg_store1 store1)\n+ uint32_t mtx, uintptr_t ra, stg_store1 store1)\n {\n int mmu_idx = arm_env_mmu_index(env);\n uint8_t *mem;\n@@ -376,17 +390,20 @@ static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,\n /* Store if page supports tags. */\n if (mem) {\n store1(ptr, mem, allocation_tag_from_addr(xt));\n+ } else if (mtx) {\n+ canonical_tag_write_fail(env, ptr, ra);\n }\n }\n \n-void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n+void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx)\n {\n- do_stg(env, ptr, xt, GETPC(), store_tag1);\n+ do_stg(env, ptr, xt, mtx, GETPC(), store_tag1);\n }\n \n-void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n+void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt,\n+ uint32_t mtx)\n {\n- do_stg(env, ptr, xt, GETPC(), store_tag1_parallel);\n+ do_stg(env, ptr, xt, mtx, GETPC(), store_tag1_parallel);\n }\n \n void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)\n@@ -399,7 +416,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)\n }\n \n static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,\n- uintptr_t ra, stg_store1 store1)\n+ uint32_t mtx, uintptr_t ra, stg_store1 store1)\n {\n int mmu_idx = arm_env_mmu_index(env);\n int tag = allocation_tag_from_addr(xt);\n@@ -422,9 +439,13 @@ static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,\n /* Store if page(s) support tags. */\n if (mem1) {\n store1(TAG_GRANULE, mem1, tag);\n+ } else if (mtx) {\n+ canonical_tag_write_fail(env, ptr, ra);\n }\n if (mem2) {\n store1(0, mem2, tag);\n+ } else if (mtx) {\n+ canonical_tag_write_fail(env, ptr + TAG_GRANULE, ra);\n }\n } else {\n /* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */\n@@ -433,18 +454,23 @@ static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,\n if (mem1) {\n tag |= tag << 4;\n qatomic_set(mem1, tag);\n+ } else if (mtx) {\n+ /* Writing tags to canonically tagged memory region: faults */\n+ canonical_tag_write_fail(env, ptr, ra);\n+ return;\n }\n }\n }\n \n-void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n+void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt, uint32_t mtx)\n {\n- do_st2g(env, ptr, xt, GETPC(), store_tag1);\n+ do_st2g(env, ptr, xt, mtx, GETPC(), store_tag1);\n }\n \n-void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)\n+void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt,\n+ uint32_t mtx)\n {\n- do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel);\n+ do_st2g(env, ptr, xt, mtx, GETPC(), store_tag1_parallel);\n }\n \n void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)\n@@ -554,7 +580,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr, uint32_t mtx)\n return ret << shift;\n }\n \n-void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)\n+void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val, uint32_t mtx)\n {\n int mmu_idx = arm_env_mmu_index(env);\n uintptr_t ra = GETPC();\n@@ -574,6 +600,10 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)\n * and if the OS has enabled access to the tags.\n */\n if (!tag_mem) {\n+ /* Storing tags to canonically tagged region: fault. */\n+ if (mtx) {\n+ canonical_tag_write_fail(env, ptr, ra);\n+ }\n return;\n }\n \n@@ -603,7 +633,8 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)\n }\n }\n \n-void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)\n+void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val,\n+ uint32_t mtx)\n {\n uintptr_t ra = GETPC();\n int mmu_idx = arm_env_mmu_index(env);\n@@ -627,6 +658,8 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)\n if (mem) {\n int tag_pair = (val & 0xf) * 0x11;\n memset(mem, tag_pair, tag_bytes);\n+ } else if (mtx) {\n+ canonical_tag_write_fail(env, ptr, ra);\n }\n }\n \ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 5fbc54de4b..68f476621a 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -3031,7 +3031,8 @@ static void handle_sys(DisasContext *s, bool isread,\n /* Extract the tag from the register to match STZGM. */\n tag = tcg_temp_new_i64();\n tcg_gen_shri_i64(tag, tcg_rt, 56);\n- gen_helper_stzgm_tags(tcg_env, clean_addr, tag);\n+ gen_helper_stzgm_tags(tcg_env, clean_addr, tag,\n+ tcg_constant_i32(s->mtx));\n }\n }\n return;\n@@ -3048,7 +3049,8 @@ static void handle_sys(DisasContext *s, bool isread,\n /* Extract the tag from the register to match STZGM. */\n tag = tcg_temp_new_i64();\n tcg_gen_shri_i64(tag, tcg_rt, 56);\n- gen_helper_stzgm_tags(tcg_env, clean_addr, tag);\n+ gen_helper_stzgm_tags(tcg_env, clean_addr, tag,\n+ tcg_constant_i32(s->mtx));\n }\n }\n return;\n@@ -3865,9 +3867,11 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair *a)\n /* Perform the tag store, if tag access enabled. */\n if (s->ata[0]) {\n if (tb_cflags(s->base.tb) & CF_PARALLEL) {\n- gen_helper_stg_parallel(tcg_env, dirty_addr, dirty_addr);\n+ gen_helper_stg_parallel(tcg_env, dirty_addr, dirty_addr,\n+ tcg_constant_i32(s->mtx));\n } else {\n- gen_helper_stg(tcg_env, dirty_addr, dirty_addr);\n+ gen_helper_stg(tcg_env, dirty_addr, dirty_addr,\n+ tcg_constant_i32(s->mtx));\n }\n }\n \n@@ -4647,7 +4651,7 @@ static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a)\n tcg_rt = cpu_reg(s, a->rt);\n \n if (s->ata[0]) {\n- gen_helper_stzgm_tags(tcg_env, addr, tcg_rt);\n+ gen_helper_stzgm_tags(tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));\n }\n /*\n * The non-tags portion of STZGM is mostly like DC_ZVA,\n@@ -4679,7 +4683,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)\n tcg_rt = cpu_reg(s, a->rt);\n \n if (s->ata[0]) {\n- gen_helper_stgm(tcg_env, addr, tcg_rt);\n+ gen_helper_stgm(tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));\n } else {\n MMUAccessType acc = MMU_DATA_STORE;\n int size = 4 << s->gm_blocksize;\n@@ -4795,15 +4799,17 @@ static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is_pair)\n }\n } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {\n if (is_pair) {\n- gen_helper_st2g_parallel(tcg_env, addr, tcg_rt);\n+ gen_helper_st2g_parallel(tcg_env, addr, tcg_rt,\n+ tcg_constant_i32(s->mtx));\n } else {\n- gen_helper_stg_parallel(tcg_env, addr, tcg_rt);\n+ gen_helper_stg_parallel(tcg_env, addr, tcg_rt,\n+ tcg_constant_i32(s->mtx));\n }\n } else {\n if (is_pair) {\n- gen_helper_st2g(tcg_env, addr, tcg_rt);\n+ gen_helper_st2g(tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));\n } else {\n- gen_helper_stg(tcg_env, addr, tcg_rt);\n+ gen_helper_stg(tcg_env, addr, tcg_rt, tcg_constant_i32(s->mtx));\n }\n }\n \n", "prefixes": [ "v5", "10/15" ] }