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GET /api/1.1/patches/2232505/?format=api
{ "id": 2232505, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232505/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-2-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-2-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:35", "name": "[v5,02/15] target/arm: add TCSO bitmasks to SCTLR", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bbf6ca9ffdbffb8f6e0158ec762d249d37850840", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-2-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232505/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232505/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ICosAELS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-2-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=3108;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=Hr6ldUvaVhbV5Q3m2e++qMNZ7Ztg5TNxADdFaQMSu2Y=;\n b=FEO+LvrHwlPxeLgVrBMIli3a/aw4g4mNK63fxcjijA7/j/rsiLH+r/kvLSQOck6XTMBWfo/rP\n Q6bpSEF8WWuBgtC3Li/TcZIZrMgWeJJ0IyuAsOy0i6S6PHfOnEvjyAU", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::834;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x834.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "These are the bitmasks used to control the FEAT_MTE_STORE_ONLY feature.\nThey are now named and setting these fields of SCTLR is ignored if MTE\nor MTE4 is disabled, as per convention.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.h | 2 ++\n target/arm/helper.c | 20 ++++++++++++++------\n 3 files changed, 21 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex c1f2336055..4d130b4b2b 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1154,6 +1154,11 @@ static inline bool isar_feature_aa64_mteperm(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTEPERM) >= 1;\n }\n \n+static inline bool isar_feature_aa64_mte_store_only(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, MTESTOREONLY) == 1;\n+}\n+\n static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex be14a47c35..9010491235 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1478,6 +1478,8 @@ void pmu_init(ARMCPU *cpu);\n #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */\n #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */\n #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */\n+#define SCTLR_TCSO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */\n+#define SCTLR_TCSO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */\n #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */\n #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */\n #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7e7677a584..ddf44f4306 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -3274,12 +3274,20 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,\n \n /* ??? Lots of these bits are not implemented. */\n \n- if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {\n- if (ri->opc1 == 6) { /* SCTLR_EL3 */\n- value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);\n- } else {\n- value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |\n- SCTLR_ATA0 | SCTLR_ATA);\n+ if (ri->state == ARM_CP_STATE_AA64) {\n+ if (!cpu_isar_feature(aa64_mte, cpu)) {\n+ if (ri->opc1 == 6) { /* SCTLR_EL3 */\n+ value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA | SCTLR_TCSO);\n+ } else {\n+ value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |\n+ SCTLR_ATA0 | SCTLR_ATA | SCTLR_TCSO | SCTLR_TCSO0);\n+ }\n+ } else if (!cpu_isar_feature(aa64_mte_store_only, cpu)) { /* not mte4 */\n+ if (ri->opc1 == 6) { /* SCTLR_EL3 */\n+ value &= ~SCTLR_TCSO;\n+ } else {\n+ value &= ~(SCTLR_TCSO | SCTLR_TCSO0);\n+ }\n }\n }\n \n", "prefixes": [ "v5", "02/15" ] }