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GET /api/1.1/patches/2232504/?format=api
{ "id": 2232504, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-3-232a648e63c6@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-feat-mte4-v5-3-232a648e63c6@gmail.com>", "date": "2026-05-04T15:50:36", "name": "[v5,03/15] target/arm: mte_check unemitted on STORE_ONLY load", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40fafd0d3f67176f1041e0139507ec6472d50111", "submitter": { "id": 91863, "url": "http://patchwork.ozlabs.org/api/1.1/people/91863/?format=api", "name": "Gabriel Brookman", "email": "brookmangabriel@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504-feat-mte4-v5-3-232a648e63c6@gmail.com/mbox/", "series": [ { "id": 502688, "url": "http://patchwork.ozlabs.org/api/1.1/series/502688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502688", "date": "2026-05-04T15:50:33", "name": "target/arm: add support for MTE4", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502688/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232504/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232504/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ZviQ+9Jb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-feat-mte4-v5-3-232a648e63c6@gmail.com>", "References": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "In-Reply-To": "<20260504-feat-mte4-v5-0-232a648e63c6@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Laurent Vivier <laurent@vivier.eu>,\n Gabriel Brookman <brookmangabriel@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777909867; l=4552;\n i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id;\n bh=yYLwhnBFaPvQITdtme0stFkgyfXUhCnT3IJ2ErgYUVs=;\n b=2EfF8uuWTh5e2J7Kby47OOAx9fZIdy/3AVZgcT6lIsN+4yiVOIy4lAdWvtV34sxRglSB7vtMO\n 9okfSeCETpOAkleM5L8bes6esipF/y55bUadu8AJRqW0+taXA5y0AFs", "X-Developer-Key": "i=brookmangabriel@gmail.com; a=ed25519;\n pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw=", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::832;\n envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x832.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This feature disables generation of the mte check helper on loads when\nSTORE_ONLY tag checking mode is enabled.\n\nSigned-off-by: Gabriel Brookman <brookmangabriel@gmail.com>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 2 ++\n target/arm/tcg/hflags.c | 12 ++++++++++++\n target/arm/tcg/translate-a64.c | 8 ++++++--\n target/arm/tcg/translate.h | 2 ++\n 4 files changed, 22 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 9010491235..706ade5784 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -2527,6 +2527,8 @@ FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2)\n FIELD(TBFLAG_A64, GCS_EN, 41, 1)\n FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1)\n FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2)\n+FIELD(TBFLAG_A64, MTE_STORE_ONLY, 45, 1)\n+FIELD(TBFLAG_A64, MTE0_STORE_ONLY, 46, 1)\n \n /*\n * Helpers for using the above. Note that only the A64 accessors use\ndiff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c\nindex 7e6f8d3647..75c55b1a6d 100644\n--- a/target/arm/tcg/hflags.c\n+++ b/target/arm/tcg/hflags.c\n@@ -423,6 +423,15 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n */\n DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);\n }\n+ /*\n+ * Repeat for MTE_STORE_ONLY\n+ */\n+ if ((el == 0 ? SCTLR_TCSO0 : SCTLR_TCSO) & sctlr) {\n+ DP_TBFLAG_A64(flags, MTE_STORE_ONLY, 1);\n+ if (!EX_TBFLAG_A64(flags, UNPRIV)) {\n+ DP_TBFLAG_A64(flags, MTE0_STORE_ONLY, 1);\n+ }\n+ }\n }\n }\n /* And again for unprivileged accesses, if required. */\n@@ -432,6 +441,9 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,\n && (sctlr & SCTLR_TCF0)\n && allocation_tag_access_enabled(env, 0, sctlr)) {\n DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);\n+ if (SCTLR_TCSO0 & sctlr) {\n+ DP_TBFLAG_A64(flags, MTE0_STORE_ONLY, 1);\n+ }\n }\n /*\n * For unpriv tag-setting accesses we also need ATA0. Again, in\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 9a27c4c6ec..ce6249649a 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -302,7 +302,8 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr,\n MemOp memop, bool is_unpriv,\n int core_idx)\n {\n- if (tag_checked && s->mte_active[is_unpriv]) {\n+ if (tag_checked && s->mte_active[is_unpriv] &&\n+ (is_write || !s->mte_store_only[is_unpriv])) {\n TCGv_i64 ret;\n int desc = 0;\n \n@@ -334,7 +335,8 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,\n TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,\n bool tag_checked, int total_size, MemOp single_mop)\n {\n- if (tag_checked && s->mte_active[0]) {\n+ if (tag_checked && s->mte_active[0] &&\n+ (is_write || !s->mte_store_only[0])) {\n TCGv_i64 ret;\n int desc = 0;\n \n@@ -10697,6 +10699,8 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n dc->ata[1] = EX_TBFLAG_A64(tb_flags, ATA0);\n dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE);\n dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);\n+ dc->mte_store_only[0] = EX_TBFLAG_A64(tb_flags, MTE_STORE_ONLY);\n+ dc->mte_store_only[1] = EX_TBFLAG_A64(tb_flags, MTE0_STORE_ONLY);\n dc->pstate_sm = EX_TBFLAG_A64(tb_flags, PSTATE_SM);\n dc->pstate_za = EX_TBFLAG_A64(tb_flags, PSTATE_ZA);\n dc->sme_trap_nonstreaming = EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTREAMING);\ndiff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 77fdc5f3a1..c74a4f6675 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -140,6 +140,8 @@ typedef struct DisasContext {\n bool ata[2];\n /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */\n bool mte_active[2];\n+ /* True if v8.5-MTE tag checks disabled for reads; index with is_unpriv. */\n+ bool mte_store_only[2];\n /* True with v8.5-BTI and SCTLR_ELx.BT* set. */\n bool bt;\n /* True if any CP15 access is trapped by HSTR_EL2 */\n", "prefixes": [ "v5", "03/15" ] }