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GET /api/1.1/patches/2232314/?format=api
{ "id": 2232314, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232314/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com>", "date": "2026-05-04T10:48:42", "name": "[v2,1/2] dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b4630f3bd9dc16a5900057ad1a43508a0f5dac83", "submitter": { "id": 93282, "url": "http://patchwork.ozlabs.org/api/1.1/people/93282/?format=api", "name": "Komal Bajaj", "email": "komal.bajaj@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com/mbox/", "series": [ { "id": 502642, "url": "http://patchwork.ozlabs.org/api/1.1/series/502642/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502642", "date": "2026-05-04T10:48:41", "name": "pinctrl: qcom: Add support for Qualcomm Shikra SoC", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502642/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232314/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232314/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-36039-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=iXIhppIg;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=WiPTwtQX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-shikra-pinctrl-v2-1-14e9dcc2d685@oss.qualcomm.com>", "References": "<20260504-shikra-pinctrl-v2-0-14e9dcc2d685@oss.qualcomm.com>", "In-Reply-To": "<20260504-shikra-pinctrl-v2-0-14e9dcc2d685@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Richard Cochran <richardcochran@gmail.com>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org, Komal Bajaj <komal.bajaj@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777891727; l=4446;\n i=komal.bajaj@oss.qualcomm.com; s=20250710; h=from:subject:message-id;\n bh=4L9GSadaTqjS847eLA+jgX3kru06L5o3Zua4WBwh3Bs=;\n b=hCr9Bt3CEH+/nEzT5GTj0Qf3eoUBVbeEy5riyuXTkejAUR96lvx1n7PxuNy9rl2ka4dirsAWI\n T/XAjjE5b2FCTwzKYVqkFY0PrUeE3g61WftANgo+R8S9sMf9RNdb7Jo", "X-Developer-Key": "i=komal.bajaj@oss.qualcomm.com; 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Shikra TLMM block\n+\n+maintainers:\n+ - Komal Bajaj <komal.bajaj@oss.qualcomm.com>\n+\n+description: |\n+ Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,shikra-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 83\n+\n+ gpio-line-names:\n+ maxItems: 166\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-shikra-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$\"\n+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,\n+ sdc2_clk, sdc2_cmd, sdc2_data ]\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,\n+ atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,\n+ cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,\n+ dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,\n+ emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,\n+ emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,\n+ i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,\n+ mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,\n+ nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,\n+ phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,\n+ qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,\n+ qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,\n+ qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,\n+ qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,\n+ ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,\n+ tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,\n+ vfr, vsense_trigger_mirnat, wlan ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@500000 {\n+ compatible = \"qcom,shikra-tlmm\";\n+ reg = <0x00500000 0x800000>;\n+\n+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ gpio-ranges = <&tlmm 0 0 166>;\n+\n+ qup-uart0-default-state {\n+ pins = \"gpio0\", \"gpio1\";\n+ function = \"qup0_se1\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n", "prefixes": [ "v2", "1/2" ] }