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GET /api/1.1/patches/2232305/?format=api
{ "id": 2232305, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2232305/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com>", "date": "2026-05-04T10:07:25", "name": "[v4,1/2] dt-bindings: pinctrl: describe the Qualcomm nord-tlmm", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bd387aa78a630ad40fee9a6871271be213c45823", "submitter": { "id": 92196, "url": "http://patchwork.ozlabs.org/api/1.1/people/92196/?format=api", "name": "Bartosz Golaszewski", "email": "bartosz.golaszewski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com/mbox/", "series": [ { "id": 502635, "url": "http://patchwork.ozlabs.org/api/1.1/series/502635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502635", "date": "2026-05-04T10:07:24", "name": "pinctrl: qcom: add support for the TLMM controller on Nord platforms", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502635/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2232305/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2232305/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-36035-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ihFTx8jy;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Y1L7zw+E;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com>", "References": "<20260504-nord-tlmm-v4-0-ccaa731ee8b3@oss.qualcomm.com>", "In-Reply-To": "<20260504-nord-tlmm-v4-0-ccaa731ee8b3@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Richard Cochran <richardcochran@gmail.com>,\n Bartosz Golaszewski <brgl@kernel.org>,\n Shawn Guo <shengchao.guo@oss.qualcomm.com>,\n Arnd Bergmann <arnd@arndb.de>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org,\n Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=6088;\n i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id;\n bh=trMfGHSt7GP5rCiBhDJR31ViCd04lGLClOnUXczfWAE=;\n b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBp+G/lntquQ/FJlrPT2ekNP4Wlia3Jwa71xuKBD\n JtT9StovxWJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCafhv5QAKCRAFnS7L/zaE\n w75GEACoRAvsFoAA+ft0q9vYNbjklsu0fLsrse0mjySd7qXxrVhCRS1gkrGYOwz83y15+BCkaAA\n oMnY7oJt+33SL1v9EX6kGT/fmYIyg6vx67Sqa1tYWyFI59vwWd/y4lZbpMsVJ5Wr4Vo8C85jgwz\n vWx/ZVIzMyyqtjfjvxmKkGcFTjLp6kEx44RlUkcXCM3UL7XRm5KixM6oj9UFgszu3lE8mK6oK58\n akJFOfXSCVec2/6Eb4ES5SS728bQY4UILGviMwuFa5qAYeutn41qAq8jk15/1bgIEQFAPeKj4mu\n i2wDe0Bz1jQdCRiBedP41ql3Kov/PdYu9yGbhVqUKrFUI6YpwdzBhDX00YrvYAkWJyPN/4xr1jz\n fVcdpE76seMhx08QF2uabR980ebynCPas7eIBXdzoONGglUPoQlnUtjD3zyFPt6nBCfwRKf0PcT\n VxgveI2aDZgLyesUI/cSJkqtsBbppirov9ifUacpEx6Syf3nLpGXZtd6B5tP4OL35Yfnuq8+uxc\n K9Xl9rxCAe+qOUOVcxulOGKtjy0qg4rOz5Uj++xwFtVbBFVZI2zQPi7zmTRc4Ceutts9apirqFw\n +o+QwTe/bNFDx2Xr+0ADxQc2DsVkvH+00EEpm6iOs44BrZyfHbaUGW3NuMjDz+t2Mq9T3nmlYH1\n Vm8QyII3jh/Is+Q==", "X-Developer-Key": "i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp;\n fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772", "X-Proofpoint-ORIG-GUID": "qErVp0K9_suctY_ElAz2WTON5Rnq1Web", "X-Authority-Analysis": "v=2.4 cv=QqxuG1yd c=1 sm=1 tr=0 ts=69f86fed cx=c_pps\n a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8\n a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=Ou3KgfM3KP2cLz_BwJkA:9 a=QEXdDO2ut3YA:10\n a=a_PwQJl-kcHnX1M80qC6:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-GUID": "qErVp0K9_suctY_ElAz2WTON5Rnq1Web", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTA0MDEwNyBTYWx0ZWRfX6JdHeTow9kxs\n TDUmFDn/s1giAyfijaIwrjGDUZt3yIuzOoayrexfOhJzNx7GR+uDJ3H7WO2inqdDhuMxQFmQmyA\n ZVQClosPYIzP2hlMmqnv7dTCfpeqCWBTcTuVusjOEipkpS9/F1enP11+EdA/UDr4xMUIeonvCwD\n gqk1sPcwOs2TQ7p7/tGzWlh5HZIGRIOODViZMb7EZDTWO4ojyT57/sX/bW+7GRHGHwjnbbWwudg\n 8lFzIrHsSgsIe3FBctEG6X/k6N6oukeDL3AoPgWCJa6zdpqsSJGf1StXooykZkixdXxuzZl/XHy\n tH/BlCoUlO7phy/TTOHGotkFEetvIuA9E6ZWkxCjK1O2X3FPNkEENNM0eDYuPtfQwdFXn8+o3D7\n 05NR0CWQKlPOtuYGbFEGZnt7sbMFpESKC52cXL2m/G24uICfB4BRUzYtAvdKUtyT8aEKig7xC6I\n 3tX9255z8dhnqCtGjGg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-04_03,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0\n priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040107" }, "content": "Add a DT binding document describing the TLMM pin controller available\non the Nord platforms from Qualcomm.\n\nCo-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nSigned-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\nSigned-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>\n---\n .../bindings/pinctrl/qcom,nord-tlmm.yaml | 141 +++++++++++++++++++++\n 1 file changed, 141 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4bb511719f3130fc208011b4a8b45f4cfcde8c9b\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\n@@ -0,0 +1,141 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. SA8797P TLMM block\n+\n+maintainers:\n+ - Bartosz Golaszewski <brgl@kernel.org>\n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,nord-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 90\n+\n+ gpio-line-names:\n+ maxItems: 181\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-nord-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$\"\n+ - enum: [ ufs_reset ]\n+ minItems: 1\n+ maxItems: 16\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,\n+ aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,\n+ aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,\n+ aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,\n+ aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,\n+ aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,\n+ aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,\n+ aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,\n+ aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,\n+ aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,\n+ aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,\n+ aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,\n+ aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,\n+ aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,\n+ bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,\n+ clink_debug, dbg_out, dbg_out_clk,\n+ ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,\n+ ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,\n+ dp_rx11, dp_rx1_mute,\n+ edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,\n+ edp3_hot, edp3_lcd,\n+ emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,\n+ emac1_mdc, emac1_mdio, emac1_ptp,\n+ gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,\n+ gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,\n+ mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,\n+ mdp_vsync_p, mdp_vsync_s,\n+ pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,\n+ pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,\n+ prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,\n+ qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,\n+ qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,\n+ qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,\n+ qup2_se5, qup2_se6,\n+ sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,\n+ smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,\n+ tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,\n+ usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,\n+ usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@f100000 {\n+ compatible = \"qcom,nord-tlmm\";\n+ reg = <0x0f100000 0xc0000>;\n+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 181>;\n+ wakeup-parent = <&pdc>;\n+\n+ qup_uart15_default: qup-uart15-default-state {\n+ pins = \"gpio147\", \"gpio148\";\n+ function = \"qup2_se2\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n", "prefixes": [ "v4", "1/2" ] }