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GET /api/1.1/patches/2231890/?format=api
{ "id": 2231890, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231890/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "date": "2026-05-01T14:29:13", "name": "[4/9] iommu/arm-smmu-v3: Convert arm_smmu_cmdq_batch cmds to struct arm_smmu_cmd", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "50fbd377c539d0f1e30bdafc5bae386623bf3694", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.1/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.1/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231890/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231890/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14136-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Z+HGYcVtKWbihSScQRlIt+2G8LLyZesKUPL2TthPmqY=;\n b=krkv6MJuHNiK/eCR3t8AyzUgeyL8SyYi3o74jpZUOMUNjOsbOzCp3aZDSAS0GB1Dxes4ZIEOkEpHQoPb+bMo9nsjm4gcB3VL0UjR7eAQ0qOINIrXP5x4g7Phc6aopyQvewEuJ7lEvc0FbgVKPaurZs63mkj2MA6AJRgWI0jkQCdmIB/d71Ju2YhdjrewUf1PxvYX7a98qTCBP5mtAjbqKj1g+jwXoAo9P0lXH5yrgjGEm0c5v6kuKMe1wdjS15TJw7WepVfgmm44rfwO/p5LCdyXZS21JMGdjkGbvxkccjjZF6D+Mblyer631V12iiitlpNlFFBnpJDDS0H7UWSz6w==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 4/9] iommu/arm-smmu-v3: Convert arm_smmu_cmdq_batch cmds to\n struct arm_smmu_cmd", "Date": "Fri, 1 May 2026 11:29:13 -0300", "Message-ID": "<4-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0042.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:5b5::7) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", 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D589EeCkH6S08/uEqEldBV6gdEiMeM7AeNzNaRNkJ2fk0yfFIUrl6PJjhDt/Dv7ZrVsKCHyBdlGtmhxappj7Ym+KWdZOUcFuSvdr5ypCps1d/T4xDqehT5M4qbYhWIac/BY+lyM0h8oZfIXK5DJSZXrpcgaeaoCl8xsSsBrTX18+3sEs/AjAbKYBNIRI1UqXV9+MNiWSXAXkXK2vnvSVzDWxsg0q0/cNduTrL6zE2WiqNu4FlnXjufwZprSXKqxSz83UCl2quwYtO56b4ZPdnDyONeXaGhlIbsoMGZkldIxaP2PFyVmI/lhaYMc75DPPBtnuCUhW8Pd6OMRV8pdt5zLtVLNga9QC9SvereMv6d+fozeuqkKp9wAq2PShsc0JWPMvPFlio9G7lol8+3FoFByPjSa3iRZ7o7cDlEGC/RrAHfr0y1C5D8+HlMwkB5WqDtXcwD+nj3h3UBq2T97WubkVd2HxZfC4TrRl/DbKcbHg9ZQlJZI7zLlWqSwgBI2uvX4M2gnS6y17LT71XrSUPo1rgEXVuX93Luuk59TygeCpTwdGJCuyzAF5eOq4BljsfifUYvje+bOonMbjDF7U1j45A6XubJgUKDv1zOKQ/jdS2NOBygrpO00lv1eQp/75s0qz9A+Mw3PsbYXGrANo0oHYOdx8LrLii9B+HkDNkSw7+PRXMDsRoFrjqSqVH4FbQ4Iueay1G/0zNe6b9OmKN0z2hXPj5NNYqCbwJJsxozuPfVGyBalQtMipU//z9GQCpTy28yty9AFCtcks8XZAPypqqG35snzvsZsKTUTRfwSBekfU1ekag4M6a8gG+d7bYLR0S04xSisMSmqsxl82p94iKEH3FYzHdld0ZNLzLwNBXhTv33shg/q+K/TBHTHdH3lOP/g4HhFiuIXBVV/O29nzIV/ko7pa+j/4JhZGm3i+Zt4fRdVsfNG6qj58C3QwaiHctwQDH54dU3qUhLkN+NaQWLe90nR9iWuswDan4MQy6n4gfnOsMdg8f3SXPUCV971H6r7ab5PZOuV6behmuU+AIuWzo7G0v8w2DkpvJSA7Ec3PHfHvKxbU+ktonbnHYEXt2UgtX83Lm6x6UT2FXKFKx8sMGaLNdOK3OT3J5MG146g5bxPOe7pgejAsxUmDHmDIUmNhOjJibbIqviDApNHYOh75T/ceRwVt1uI+LLC/IhzaUccigAoaGnX/jugwq8/amfmsWq9U494m8naephjFtHFDi1Zp3PAMvsEpWy0ydW8txEeIDh2Avo05yUwcOD8u0PhEY64vaPwDYEtjc37OwnTWW9IiwCSNlUSiwXprZ79VeEqOMJvXO8ZhtG6ougSHhSdTLoHvFuglTv/jyU2Rm9/1R9SdqxHI3OK+Qp4ap1f3DG/WmyTpoyuJKkaP0wiYcENnhwkfc1Q5dorvq5aWojvY2ZUBLZGirYISDWPDH17tYrwtu+0yq4muaBDtJYZ65PnrMPlfaG61pPpn1f7Gd3x71aPD7pSFs9aZPsb3f5gdvZhaC+ClqsAHGoMPVbGH4/kANGou3wrbGDfNNM0U8nSBqOeGLxjDB6n3Kved8uQMrsYA3HULDh/MJtCh2SYEr9MmYBXDsPzsZd7tMYqiGlrUhse4yXKUoynGn2o7ydA+ZP0OT18eewNtv1nIsDK0jiSENm+EcPCJitKaxLSOYRY/9TXU2G123gheEzyLLozCJYTugWTZGDMH8La8", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 914e0347-2dcd-4d78-a739-08dea78e0938", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:22.4244\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n pmlxebjwlpApYCsLo4v7VwTSzSuYwZcyZzAobo1dfNsoeMq7Uz1Lq4Co9u7LM5Sr", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR12MB9216" }, "content": "Convert the batch's type to also get the remaining helper functions to\nuse the new type and complete replacing naked u64s with the new struct.\n\nThe low-level queue_write()/queue_read()/queue_remove_raw() functions\nremain u64-based since they are shared by event and PRI queues which\nhave different entry sizes.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 24 +++---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 ++++++++++---------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +-\n .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 8 +-\n 4 files changed, 58 insertions(+), 53 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c\nindex ddae0b07c76b50..1e9f7d2de34414 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c\n@@ -300,7 +300,7 @@ static int arm_vsmmu_vsid_to_sid(struct arm_vsmmu *vsmmu, u32 vsid, u32 *sid)\n /* This is basically iommu_viommu_arm_smmuv3_invalidate in u64 for conversion */\n struct arm_vsmmu_invalidation_cmd {\n \tunion {\n-\t\tu64 cmd[2];\n+\t\tstruct arm_smmu_cmd cmd;\n \t\tstruct iommu_viommu_arm_smmuv3_invalidate ucmd;\n \t};\n };\n@@ -316,32 +316,32 @@ static int arm_vsmmu_convert_user_cmd(struct arm_vsmmu *vsmmu,\n \t\t\t\t struct arm_vsmmu_invalidation_cmd *cmd)\n {\n \t/* Commands are le64 stored in u64 */\n-\tcmd->cmd[0] = le64_to_cpu(cmd->ucmd.cmd[0]);\n-\tcmd->cmd[1] = le64_to_cpu(cmd->ucmd.cmd[1]);\n+\tcmd->cmd.data[0] = le64_to_cpu(cmd->ucmd.cmd[0]);\n+\tcmd->cmd.data[1] = le64_to_cpu(cmd->ucmd.cmd[1]);\n \n-\tswitch (cmd->cmd[0] & CMDQ_0_OP) {\n+\tswitch (cmd->cmd.data[0] & CMDQ_0_OP) {\n \tcase CMDQ_OP_TLBI_NSNH_ALL:\n \t\t/* Convert to NH_ALL */\n-\t\tcmd->cmd[0] = CMDQ_OP_TLBI_NH_ALL |\n+\t\tcmd->cmd.data[0] = CMDQ_OP_TLBI_NH_ALL |\n \t\t\t FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid);\n-\t\tcmd->cmd[1] = 0;\n+\t\tcmd->cmd.data[1] = 0;\n \t\tbreak;\n \tcase CMDQ_OP_TLBI_NH_VA:\n \tcase CMDQ_OP_TLBI_NH_VAA:\n \tcase CMDQ_OP_TLBI_NH_ALL:\n \tcase CMDQ_OP_TLBI_NH_ASID:\n-\t\tcmd->cmd[0] &= ~CMDQ_TLBI_0_VMID;\n-\t\tcmd->cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid);\n+\t\tcmd->cmd.data[0] &= ~CMDQ_TLBI_0_VMID;\n+\t\tcmd->cmd.data[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid);\n \t\tbreak;\n \tcase CMDQ_OP_ATC_INV:\n \tcase CMDQ_OP_CFGI_CD:\n \tcase CMDQ_OP_CFGI_CD_ALL: {\n-\t\tu32 sid, vsid = FIELD_GET(CMDQ_CFGI_0_SID, cmd->cmd[0]);\n+\t\tu32 sid, vsid = FIELD_GET(CMDQ_CFGI_0_SID, cmd->cmd.data[0]);\n \n \t\tif (arm_vsmmu_vsid_to_sid(vsmmu, vsid, &sid))\n \t\t\treturn -EIO;\n-\t\tcmd->cmd[0] &= ~CMDQ_CFGI_0_SID;\n-\t\tcmd->cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid);\n+\t\tcmd->cmd.data[0] &= ~CMDQ_CFGI_0_SID;\n+\t\tcmd->cmd.data[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid);\n \t\tbreak;\n \t}\n \tdefault:\n@@ -386,7 +386,7 @@ int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu,\n \t\t\tcontinue;\n \n \t\t/* FIXME always uses the main cmdq rather than trying to group by type */\n-\t\tret = arm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, last->cmd,\n+\t\tret = arm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, &last->cmd,\n \t\t\t\t\t\t cur - last, true);\n \t\tif (ret) {\n \t\t\tcur--;\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex 67d23e9c54804e..b3ef001ce80d23 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -268,9 +268,12 @@ static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)\n }\n \n /* High-level queue accessors */\n-static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)\n+static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n+\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n {\n-\tmemset(cmd, 0, 1 << CMDQ_ENT_SZ_SHIFT);\n+\tu64 *cmd = cmd_out->data;\n+\n+\tmemset(cmd_out, 0, sizeof(*cmd_out));\n \tcmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);\n \n \tswitch (ent->opcode) {\n@@ -390,7 +393,8 @@ static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu,\n \treturn smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV;\n }\n \n-static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,\n+static void arm_smmu_cmdq_build_sync_cmd(struct arm_smmu_cmd *cmd,\n+\t\t\t\t\t struct arm_smmu_device *smmu,\n \t\t\t\t\t struct arm_smmu_cmdq *cmdq, u32 prod)\n {\n \tstruct arm_smmu_queue *q = &cmdq->q;\n@@ -409,7 +413,8 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu,\n \n \tarm_smmu_cmdq_build_cmd(cmd, &ent);\n \tif (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))\n-\t\tu64p_replace_bits(cmd, CMDQ_SYNC_0_CS_NONE, CMDQ_SYNC_0_CS);\n+\t\tu64p_replace_bits(&cmd->data[0], CMDQ_SYNC_0_CS_NONE,\n+\t\t\t\t CMDQ_SYNC_0_CS);\n }\n \n void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n@@ -422,9 +427,8 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n \t\t[CMDQ_ERR_CERROR_ATC_INV_IDX]\t= \"ATC invalidate timeout\",\n \t};\n \tstruct arm_smmu_queue *q = &cmdq->q;\n-\n \tint i;\n-\tu64 cmd[CMDQ_ENT_DWORDS];\n+\tstruct arm_smmu_cmd cmd;\n \tu32 cons = readl_relaxed(q->cons_reg);\n \tu32 idx = FIELD_GET(CMDQ_CONS_ERR, cons);\n \tstruct arm_smmu_cmdq_ent cmd_sync = {\n@@ -457,17 +461,18 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu,\n \t * We may have concurrent producers, so we need to be careful\n \t * not to touch any of the shadow cmdq state.\n \t */\n-\tqueue_read(cmd, Q_ENT(q, cons), q->ent_dwords);\n+\tqueue_read(cmd.data, Q_ENT(q, cons), q->ent_dwords);\n \tdev_err(smmu->dev, \"skipping command in error state:\\n\");\n-\tfor (i = 0; i < ARRAY_SIZE(cmd); ++i)\n-\t\tdev_err(smmu->dev, \"\\t0x%016llx\\n\", (unsigned long long)cmd[i]);\n+\tfor (i = 0; i < ARRAY_SIZE(cmd.data); ++i)\n+\t\tdev_err(smmu->dev, \"\\t0x%016llx\\n\", (unsigned long long)cmd.data[i]);\n \n \t/* Convert the erroneous command into a CMD_SYNC */\n-\tarm_smmu_cmdq_build_cmd(cmd, &cmd_sync);\n+\tarm_smmu_cmdq_build_cmd(&cmd, &cmd_sync);\n \tif (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq))\n-\t\tu64p_replace_bits(cmd, CMDQ_SYNC_0_CS_NONE, CMDQ_SYNC_0_CS);\n+\t\tu64p_replace_bits(&cmd.data[0], CMDQ_SYNC_0_CS_NONE,\n+\t\t\t\t CMDQ_SYNC_0_CS);\n \n-\tqueue_write(Q_ENT(q, cons), cmd, q->ent_dwords);\n+\tqueue_write(Q_ENT(q, cons), cmd.data, q->ent_dwords);\n }\n \n static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)\n@@ -767,7 +772,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu,\n \treturn __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq);\n }\n \n-static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds,\n+static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq,\n+\t\t\t\t\tstruct arm_smmu_cmd *cmds,\n \t\t\t\t\tu32 prod, int n)\n {\n \tint i;\n@@ -777,10 +783,9 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds,\n \t};\n \n \tfor (i = 0; i < n; ++i) {\n-\t\tu64 *cmd = &cmds[i * CMDQ_ENT_DWORDS];\n-\n \t\tprod = queue_inc_prod_n(&llq, i);\n-\t\tqueue_write(Q_ENT(&cmdq->q, prod), cmd, CMDQ_ENT_DWORDS);\n+\t\tqueue_write(Q_ENT(&cmdq->q, prod), cmds[i].data,\n+\t\t\t ARRAY_SIZE(cmds[i].data));\n \t}\n }\n \n@@ -801,10 +806,11 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds,\n * CPU will appear before any of the commands from the other CPU.\n */\n int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n-\t\t\t\tstruct arm_smmu_cmdq *cmdq, u64 *cmds, int n,\n+\t\t\t\tstruct arm_smmu_cmdq *cmdq,\n+\t\t\t\tstruct arm_smmu_cmd *cmds, int n,\n \t\t\t\tbool sync)\n {\n-\tu64 cmd_sync[CMDQ_ENT_DWORDS];\n+\tstruct arm_smmu_cmd cmd_sync;\n \tu32 prod;\n \tunsigned long flags;\n \tbool owner;\n@@ -847,8 +853,9 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n \tarm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n);\n \tif (sync) {\n \t\tprod = queue_inc_prod_n(&llq, n);\n-\t\tarm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod);\n-\t\tqueue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS);\n+\t\tarm_smmu_cmdq_build_sync_cmd(&cmd_sync, smmu, cmdq, prod);\n+\t\tqueue_write(Q_ENT(&cmdq->q, prod), cmd_sync.data,\n+\t\t\t ARRAY_SIZE(cmd_sync.data));\n \n \t\t/*\n \t\t * In order to determine completion of our CMD_SYNC, we must\n@@ -925,7 +932,7 @@ static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n \t\t\t\t bool sync)\n {\n \treturn arm_smmu_cmdq_issue_cmdlist(\n-\t\tsmmu, arm_smmu_get_cmdq(smmu, cmd), cmd->data, 1, sync);\n+\t\tsmmu, arm_smmu_get_cmdq(smmu, cmd), cmd, 1, sync);\n }\n \n static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,\n@@ -954,7 +961,7 @@ static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,\n {\n \tstruct arm_smmu_cmd cmd;\n \n-\tarm_smmu_cmdq_build_cmd(cmd.data, ent);\n+\tarm_smmu_cmdq_build_cmd(&cmd, ent);\n \tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n }\n \n@@ -966,9 +973,8 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n \t\t\t (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC);\n \tstruct arm_smmu_cmd cmd;\n \tbool unsupported_cmd;\n-\tint index;\n \n-\tif (unlikely(arm_smmu_cmdq_build_cmd(cmd.data, ent))) {\n+\tif (unlikely(arm_smmu_cmdq_build_cmd(&cmd, ent))) {\n \t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n \t\t\t ent->opcode);\n \t\treturn;\n@@ -987,9 +993,7 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n \t\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n \t}\n \n-\tindex = cmds->num * CMDQ_ENT_DWORDS;\n-\tmemcpy(&cmds->cmds[index], cmd.data, sizeof(cmd.data));\n-\tcmds->num++;\n+\tcmds->cmds[cmds->num++] = cmd;\n }\n \n static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,\n@@ -1025,7 +1029,7 @@ static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused\n \t\tbreak;\n \t}\n \n-\tarm_smmu_cmdq_build_cmd(hw_cmd.data, &cmd);\n+\tarm_smmu_cmdq_build_cmd(&hw_cmd, &cmd);\n \tarm_smmu_cmdq_issue_cmd(master->smmu, &hw_cmd);\n \n \t/*\n@@ -1865,7 +1869,7 @@ static void arm_smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer)\n \t};\n \tstruct arm_smmu_cmd cmd;\n \n-\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n+\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd);\n }\n \n@@ -1899,7 +1903,7 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid,\n \t\t\t\t\t } };\n \t\tstruct arm_smmu_cmd prefetch_cmd;\n \n-\t\tarm_smmu_cmdq_build_cmd(prefetch_cmd.data, &prefetch_ent);\n+\t\tarm_smmu_cmdq_build_cmd(&prefetch_cmd, &prefetch_ent);\n \t\tarm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);\n \t}\n }\n@@ -2339,7 +2343,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)\n \t\t};\n \t\tstruct arm_smmu_cmd cmd;\n \n-\t\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n+\t\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n \t\tarm_smmu_cmdq_issue_cmd(smmu, &cmd);\n \t}\n }\n@@ -3462,7 +3466,7 @@ static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n \t}\n \n \tcmd.opcode = inv->nsize_opcode;\n-\tarm_smmu_cmdq_build_cmd(hw_cmd.data, &cmd);\n+\tarm_smmu_cmdq_build_cmd(&hw_cmd, &cmd);\n \tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &hw_cmd);\n }\n \n@@ -4875,18 +4879,18 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)\n \n \t/* Invalidate any cached configuration */\n \tent.opcode = CMDQ_OP_CFGI_ALL;\n-\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n+\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \n \t/* Invalidate any stale TLB entries */\n \tif (smmu->features & ARM_SMMU_FEAT_HYP) {\n \t\tent.opcode = CMDQ_OP_TLBI_EL2_ALL;\n-\t\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n+\t\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n \t\tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \t}\n \n \tent.opcode = CMDQ_OP_TLBI_NSNH_ALL;\n-\tarm_smmu_cmdq_build_cmd(cmd.data, &ent);\n+\tarm_smmu_cmdq_build_cmd(&cmd, &ent);\n \tarm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd);\n \n \t/* Event queue */\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 6d73f6b63e64a9..1fe6917448b774 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -651,7 +651,7 @@ static inline bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq,\n }\n \n struct arm_smmu_cmdq_batch {\n-\tu64\t\t\t\tcmds[CMDQ_BATCH_ENTRIES * CMDQ_ENT_DWORDS];\n+\tstruct arm_smmu_cmd\t\tcmds[CMDQ_BATCH_ENTRIES];\n \tstruct arm_smmu_cmdq\t\t*cmdq;\n \tint\t\t\t\tnum;\n };\n@@ -1148,7 +1148,8 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master,\n \t\t\t\t const struct arm_smmu_ste *target);\n \n int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,\n-\t\t\t\tstruct arm_smmu_cmdq *cmdq, u64 *cmds, int n,\n+\t\t\t\tstruct arm_smmu_cmdq *cmdq,\n+\t\t\t\tstruct arm_smmu_cmd *cmds, int n,\n \t\t\t\tbool sync);\n \n #ifdef CONFIG_ARM_SMMU_V3_SVA\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\nindex b4d8c1f2fd3878..67be62a6e7640a 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c\n@@ -427,16 +427,16 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu,\n static void tegra241_vcmdq_hw_flush_timeout(struct tegra241_vcmdq *vcmdq)\n {\n \tstruct arm_smmu_device *smmu = &vcmdq->cmdqv->smmu;\n-\tu64 cmd_sync[CMDQ_ENT_DWORDS] = {};\n+\tstruct arm_smmu_cmd cmd_sync = {};\n \n-\tcmd_sync[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) |\n-\t\t FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE);\n+\tcmd_sync.data[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) |\n+\t\t\t FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE);\n \n \t/*\n \t * It does not hurt to insert another CMD_SYNC, taking advantage of the\n \t * arm_smmu_cmdq_issue_cmdlist() that waits for the CMD_SYNC completion.\n \t */\n-\tarm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, cmd_sync, 1, true);\n+\tarm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, &cmd_sync, 1, true);\n }\n \n /* This function is for LVCMDQ, so @vcmdq must not be unmapped yet */\n", "prefixes": [ "4/9" ] }