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GET /api/1.1/patches/2231889/?format=api
{ "id": 2231889, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "date": "2026-05-01T14:29:18", "name": "[9/9] iommu/arm-smmu-v3: Directly encode TLBI commands", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e9bcfaf749e2028e351972084310c6dac12a0e00", "submitter": { "id": 79424, "url": "http://patchwork.ozlabs.org/api/1.1/people/79424/?format=api", "name": "Jason Gunthorpe", "email": "jgg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/", "series": [ { "id": 502465, "url": "http://patchwork.ozlabs.org/api/1.1/series/502465/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465", "date": "2026-05-01T14:29:09", "name": "Remove SMMUv3 struct arm_smmu_cmdq_ent", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502465/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231889/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231889/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14135-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/RYIXocgMM5PzB9N2mYiUcD0fy2ktzu64bjEhQcjwNY=;\n b=YxCen9cVoGo8yHvSSQH95jIEEbVhm74PFDF8Dw3BnlyZlnDZqBfLG0XrhZN183ehLpn0ah1FHMuYioVBlIvnx3D4LD2vSdnkDtlr2pCR71FaesJSQhyRRQ9FwVwyBWzxb2W5LrDWbdelDqb3ckF07tMMX2D2ke3GkadUS3Ifw/bD0qJdxgVAYtAfO/QUJY4tDanmtDB3RJEkIlLwx1JYbBOhFkiaDhe/LjsCveFzMWZQA8pOk1b0pBsYM0B1lti4PEXKLrzVuw8akjFLlee3IzuiMOGw/sWkVMBCjxDrKWODMjJMPGCMU5apqeVS+E3jO5HcTc2gvdp2HP9f6YP1YA==", "From": "Jason Gunthorpe <jgg@nvidia.com>", "To": "iommu@lists.linux.dev,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tJoerg Roedel <joro@8bytes.org>,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy <robin.murphy@arm.com>,\n\tThierry Reding <thierry.reding@kernel.org>,\n\tKrishna Reddy <vdumpa@nvidia.com>,\n\tWill Deacon <will@kernel.org>", "Cc": "David Matlack <dmatlack@google.com>,\n\tPasha Tatashin <pasha.tatashin@soleen.com>,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja <skhawaja@google.com>,\n\tMostafa Saleh <smostafa@google.com>", "Subject": "[PATCH 9/9] iommu/arm-smmu-v3: Directly encode TLBI commands", "Date": "Fri, 1 May 2026 11:29:18 -0300", "Message-ID": "<9-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "In-Reply-To": "<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>", "References": "", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BL1P221CA0040.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:5b5::15) To LV8PR12MB9620.namprd12.prod.outlook.com\n (2603:10b6:408:2a1::19)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", 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HmFVdSmm7lBgW7QuoH1Hl9WJTAgXAWFIhLRDIenAuYEd3duBXOuuI5fomP9bsHChh6WuqTaayw5HwMwnEtahrLk1diDJj5NDK+qHeU+uFlUfYwbXLy2fQjTIiD1tZjWjit1WI74wjgTB6+6fFzkP28N2wp6TeNBW45AiBJFzoXsOABmr6UYo/x6bLoiC56Dq1vYFZtz2fcfLLAnu8zw32EZZ9HWOqD6quxJqcL1L7vYoXsLRKLgJX6j362le4HnWNT5xgmef5UAWExILYj4QQCNIaqHaDXy70aSsa9ie4ZGIvyMifdWzwLfzBy1KYSFMcRMuuddpHiVzlnTATTgdaAtD42mmMz48GovrasT1SphHtKJkbOBVYFkFFvrLf/9XKOFDrCsHtHgnyF5qu3lP4jgpFXomDn65VRrwW63jMWGDI01YCDLHFw0jv0J0LS+sMc2ys50ItRMDIWjXRcl5O0gxUuO3XI2WekbBH9dWqCVkCda5oCr/jiL3Ipd9QTVI9ysA8Ng/UCqYbAzZaZ3ESzjbmpDp23DE70uH7J18vW9MuXxZtW9ryro8QFhjqCUaVIruiWkjLGWEhwL996PHYJjTiaSFgUSR0iINJ8Oy3zIi/z0YJz2pbJmy2cMhEQom9aw70SWyQZczPtflJByOAd+iNbu4eqetHyzfb+oCM2iCxMvTjQxTEb02303ZpYyS25MElBRwU7fDwMtzJasD8My+aSUG/RYNu0e/Dt9gwYtOy1PUhultZG9OFN4cig0U364BIo2ESD7SxYOE9nX5aAJIPooXNq0rSIEXsmqiOXLxHUYE5fgW/WaVZ8MROiKtREsac8JsPuSp0rqWH++T5H8sA9wXrJG2KObFUvDE7jrl19M52NOZXYI/JIYzxaiNHzqmyv5G4GfrthYi2QA4GAolwGiCXRBQIS6CygftKUPRja7gOtTjSH2SQA+kxK+HOTSE4iB22U5LQ5fD2hcMnVB7SSODuxpyn824Qffn+CkO0BPd+HnpsrR+Fj5Krid++21pQ2Jq4ocV+CK5VyRK8FL+mEU2C4p/L9oPOtkBGNmHNOv0PsRUlCWRszNoJRNfKxgRRkmCCFZqJY5JnS19QQGTW4041+nrvHmBFg6yKaZ1XS1IpvHgJMoVzasIzDzLl6a/LnY0rFSjBnlToZsDYGz026puYOJLR+P9qADKaP22m1XgqxtrLjL1qR8D6p78Mbhl7Y2zAOhn1DbDAemBkM+zaaebJg7q0vRxsQHmE4vkJWGpzb+9l3b6zsPMAU30slGUWWZjtohf0eUEuvKwfSs5L9v5rvhsnNUAO5WFyeAqcG21yB4nk5xEd4V2NFAxcBctiS22Xr1lHO00dBErMETpGqzfxfU9Jd6bdlI07eW3pDnw7TXL9ApRyP9y+cdxCrqVUi5yJqbhZjlLDcJb12dfDmdgJUa2E+p6zf4Pw5Jny07LkGuSfkG7mkkPLcJLgUZzxcQVjWpBe+HBFnJT3J7gNgEVUaS49D78lFyIBB5TK7uEK7gTM/ErXmNf5dh6AdCPlk9PZeuty7xLr/vDd0UH8RJuM1bWAvYNy96eJHthlX/EZV9vPbN/o1Jb1E7F21VH6+Q6QWQ+35/i9LmtW3bTaEBY0iYtYU5NzOKqVF62nz72vV2Wo/p/iGUYHGnDNnq0FEMowzCWyYkfZLUzJ/M2HkQDatHFEmHbTx/Vc54Pa5e9OY7gUCcaS42GwyXr", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b0032a06-8315-434b-3444-08dea78e07ba", "X-MS-Exchange-CrossTenant-AuthSource": "LV8PR12MB9620.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 May 2026 14:29:19.3524\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n eVD2YNOMsorvaA5kK3p1dwPRiI3CVcGdJdbHkoQu49x6csEs65gJp6r2d3LML3i6", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8096" }, "content": "TLBI is more complicated than all the other commands because the\ninvalidation loop builds a template command from the struct\narm_smmu_inv which is then expanded into many TLBI commands for the\ninvalidation.\n\nSigned-off-by: Jason Gunthorpe <jgg@nvidia.com>\n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 170 +++++++-------------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 35 ++--\n 2 files changed, 71 insertions(+), 134 deletions(-)", "diff": "diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex 8147b9cdcc6b99..9be589d14a3bd4 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -268,53 +268,6 @@ static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)\n }\n \n /* High-level queue accessors */\n-static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n-\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n-{\n-\tu64 *cmd = cmd_out->data;\n-\n-\tmemset(cmd_out, 0, sizeof(*cmd_out));\n-\tcmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode);\n-\n-\tswitch (ent->opcode) {\n-\tcase CMDQ_OP_TLBI_NH_VA:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);\n-\t\tfallthrough;\n-\tcase CMDQ_OP_TLBI_EL2_VA:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);\n-\t\tcmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;\n-\t\tbreak;\n-\tcase CMDQ_OP_TLBI_S2_IPA:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg);\n-\t\tcmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;\n-\t\tbreak;\n-\tcase CMDQ_OP_TLBI_NH_ASID:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n-\t\tfallthrough;\n-\tcase CMDQ_OP_TLBI_NH_ALL:\n-\tcase CMDQ_OP_TLBI_S12_VMALL:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);\n-\t\tbreak;\n-\tcase CMDQ_OP_TLBI_EL2_ASID:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENOENT;\n-\t}\n-\n-\treturn 0;\n-}\n-\n static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu,\n \t\t\t\t\t struct arm_smmu_cmd *cmd)\n {\n@@ -894,16 +847,6 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_smmu_device *smmu,\n \tcmds->cmdq = arm_smmu_get_cmdq(smmu, cmd);\n }\n \n-static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n-\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n-{\n-\tstruct arm_smmu_cmd cmd;\n-\n-\tarm_smmu_cmdq_build_cmd(&cmd, ent);\n-\tarm_smmu_cmdq_batch_init_cmd(smmu, cmds, &cmd);\n-}\n-\n static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu,\n \t\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n \t\t\t\t\t struct arm_smmu_cmd *cmd)\n@@ -934,21 +877,6 @@ static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu,\n \t\tarm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, &__cmd); \\\n \t})\n \n-static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu,\n-\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n-\t\t\t\t struct arm_smmu_cmdq_ent *ent)\n-{\n-\tstruct arm_smmu_cmd cmd;\n-\n-\tif (unlikely(arm_smmu_cmdq_build_cmd(&cmd, ent))) {\n-\t\tdev_warn(smmu->dev, \"ignoring unknown CMDQ opcode 0x%x\\n\",\n-\t\t\t ent->opcode);\n-\t\treturn;\n-\t}\n-\n-\tarm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, &cmd);\n-}\n-\n static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu,\n \t\t\t\t struct arm_smmu_cmdq_batch *cmds)\n {\n@@ -2450,12 +2378,14 @@ static void arm_smmu_tlb_inv_context(void *cookie)\n \n static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,\n \t\t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n-\t\t\t\t\t struct arm_smmu_cmdq_ent *cmd,\n+\t\t\t\t\t struct arm_smmu_cmd *cmd, bool leaf,\n \t\t\t\t\t unsigned long iova, size_t size,\n \t\t\t\t\t size_t granule, size_t pgsize)\n {\n \tunsigned long end = iova + size, num_pages = 0, tg = pgsize;\n+\tu64 orig_data0 = cmd->data[0];\n \tsize_t inv_range = granule;\n+\tu8 ttl = 0, tg_enc = 0;\n \n \tif (WARN_ON_ONCE(!size))\n \t\treturn;\n@@ -2464,7 +2394,7 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,\n \t\tnum_pages = size >> tg;\n \n \t\t/* Convert page size of 12,14,16 (log2) to 1,2,3 */\n-\t\tcmd->tlbi.tg = (tg - 10) / 2;\n+\t\ttg_enc = (tg - 10) / 2;\n \n \t\t/*\n \t\t * Determine what level the granule is at. For non-leaf, both\n@@ -2474,8 +2404,8 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,\n \t\t * want to use a range command, so avoid the SVA corner case\n \t\t * where both scale and num could be 0 as well.\n \t\t */\n-\t\tif (cmd->tlbi.leaf)\n-\t\t\tcmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3));\n+\t\tif (leaf)\n+\t\t\tttl = 4 - ((ilog2(granule) - 3) / (tg - 3));\n \t\telse if ((num_pages & CMDQ_TLBI_RANGE_NUM_MAX) == 1)\n \t\t\tnum_pages++;\n \t}\n@@ -2493,11 +2423,13 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,\n \n \t\t\t/* Determine the power of 2 multiple number of pages */\n \t\t\tscale = __ffs(num_pages);\n-\t\t\tcmd->tlbi.scale = scale;\n \n \t\t\t/* Determine how many chunks of 2^scale size we have */\n \t\t\tnum = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX;\n-\t\t\tcmd->tlbi.num = num - 1;\n+\n+\t\t\tcmd->data[0] = orig_data0 |\n+\t\t\t\tFIELD_PREP(CMDQ_TLBI_0_NUM, num - 1) |\n+\t\t\t\tFIELD_PREP(CMDQ_TLBI_0_SCALE, scale);\n \n \t\t\t/* range is num * 2^scale * pgsize */\n \t\t\tinv_range = num << (scale + tg);\n@@ -2506,8 +2438,17 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu,\n \t\t\tnum_pages -= num << scale;\n \t\t}\n \n-\t\tcmd->tlbi.addr = iova;\n-\t\tarm_smmu_cmdq_batch_add(smmu, cmds, cmd);\n+\t\t/*\n+\t\t * IPA has fewer bits than VA, but they are reserved in the\n+\t\t * command and something would be very broken if iova had them\n+\t\t * set.\n+\t\t */\n+\t\tcmd->data[1] = FIELD_PREP(CMDQ_TLBI_1_LEAF, leaf) |\n+\t\t\t FIELD_PREP(CMDQ_TLBI_1_TTL, ttl) |\n+\t\t\t FIELD_PREP(CMDQ_TLBI_1_TG, tg_enc) |\n+\t\t\t (iova & ~GENMASK_U64(11, 0));\n+\n+\t\tarm_smmu_cmdq_batch_add_cmd_p(smmu, cmds, cmd);\n \t\tiova += inv_range;\n \t}\n }\n@@ -2538,19 +2479,22 @@ static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t size,\n /* Used by non INV_TYPE_ATS* invalidations */\n static void arm_smmu_inv_to_cmdq_batch(struct arm_smmu_inv *inv,\n \t\t\t\t struct arm_smmu_cmdq_batch *cmds,\n-\t\t\t\t struct arm_smmu_cmdq_ent *cmd,\n+\t\t\t\t struct arm_smmu_cmd *cmd,\n+\t\t\t\t bool leaf,\n \t\t\t\t unsigned long iova, size_t size,\n \t\t\t\t unsigned int granule)\n {\n \tif (arm_smmu_inv_size_too_big(inv->smmu, size, granule)) {\n-\t\tcmd->opcode = inv->nsize_opcode;\n-\t\tarm_smmu_cmdq_batch_add(inv->smmu, cmds, cmd);\n+\t\tstruct arm_smmu_cmd nsize_cmd = *cmd;\n+\n+\t\tu64p_replace_bits(&nsize_cmd.data[0], inv->nsize_opcode,\n+\t\t\t\t CMDQ_0_OP);\n+\t\tarm_smmu_cmdq_batch_add_cmd_p(inv->smmu, cmds, &nsize_cmd);\n \t\treturn;\n \t}\n \n-\tcmd->opcode = inv->size_opcode;\n-\tarm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, iova, size, granule,\n-\t\t\t\t inv->pgsize);\n+\tarm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, leaf,\n+\t\t\t\t iova, size, granule, inv->pgsize);\n }\n \n static inline bool arm_smmu_invs_end_batch(struct arm_smmu_inv *cur,\n@@ -2585,38 +2529,39 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\t\tbreak;\n \twhile (cur != end) {\n \t\tstruct arm_smmu_device *smmu = cur->smmu;\n-\t\tstruct arm_smmu_cmdq_ent cmd = {\n-\t\t\t/*\n-\t\t\t * Pick size_opcode to run arm_smmu_get_cmdq(). This can\n-\t\t\t * be changed to nsize_opcode, which would result in the\n-\t\t\t * same CMDQ pointer.\n-\t\t\t */\n-\t\t\t.opcode = cur->size_opcode,\n-\t\t};\n+\t\t/*\n+\t\t * Pick size_opcode to run arm_smmu_get_cmdq(). This can\n+\t\t * be changed to nsize_opcode, which would result in the\n+\t\t * same CMDQ pointer.\n+\t\t */\n+\t\tstruct arm_smmu_cmd cmd =\n+\t\t\tarm_smmu_make_cmd_op(cur->size_opcode);\n \t\tstruct arm_smmu_inv *next;\n \n \t\tif (!cmds.num)\n-\t\t\tarm_smmu_cmdq_batch_init(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_init_cmd(smmu, &cmds, &cmd);\n \n \t\tswitch (cur->type) {\n \t\tcase INV_TYPE_S1_ASID:\n-\t\t\tcmd.tlbi.asid = cur->id;\n-\t\t\tcmd.tlbi.leaf = leaf;\n-\t\t\tarm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size,\n-\t\t\t\t\t\t granule);\n+\t\t\tcmd = arm_smmu_make_cmd_tlbi(cur->size_opcode,\n+\t\t\t\t\t\t cur->id, 0);\n+\t\t\tarm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, leaf,\n+\t\t\t\t\t\t iova, size, granule);\n \t\t\tbreak;\n \t\tcase INV_TYPE_S2_VMID:\n-\t\t\tcmd.tlbi.vmid = cur->id;\n-\t\t\tcmd.tlbi.leaf = leaf;\n-\t\t\tarm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size,\n-\t\t\t\t\t\t granule);\n+\t\t\tcmd = arm_smmu_make_cmd_tlbi(cur->size_opcode,\n+\t\t\t\t\t\t 0, cur->id);\n+\t\t\tarm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, leaf,\n+\t\t\t\t\t\t iova, size, granule);\n \t\t\tbreak;\n \t\tcase INV_TYPE_S2_VMID_S1_CLEAR:\n \t\t\t/* CMDQ_OP_TLBI_S12_VMALL already flushed S1 entries */\n \t\t\tif (arm_smmu_inv_size_too_big(cur->smmu, size, granule))\n \t\t\t\tbreak;\n-\t\t\tcmd.tlbi.vmid = cur->id;\n-\t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\t\tsmmu, &cmds,\n+\t\t\t\tarm_smmu_make_cmd_tlbi(cur->size_opcode, 0,\n+\t\t\t\t\t\t cur->id));\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS:\n \t\t\tarm_smmu_cmdq_batch_add_cmd(\n@@ -3359,24 +3304,21 @@ arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state)\n \n static void arm_smmu_inv_flush_iotlb_tag(struct arm_smmu_inv *inv)\n {\n-\tstruct arm_smmu_cmdq_ent cmd = {};\n-\tstruct arm_smmu_cmd hw_cmd;\n-\n \tswitch (inv->type) {\n \tcase INV_TYPE_S1_ASID:\n-\t\tcmd.tlbi.asid = inv->id;\n+\t\tarm_smmu_cmdq_issue_cmd_with_sync(\n+\t\t\tinv->smmu,\n+\t\t\tarm_smmu_make_cmd_tlbi(inv->nsize_opcode, inv->id, 0));\n \t\tbreak;\n \tcase INV_TYPE_S2_VMID:\n \t\t/* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */\n-\t\tcmd.tlbi.vmid = inv->id;\n+\t\tarm_smmu_cmdq_issue_cmd_with_sync(\n+\t\t\tinv->smmu,\n+\t\t\tarm_smmu_make_cmd_tlbi(inv->nsize_opcode, 0, inv->id));\n \t\tbreak;\n \tdefault:\n \t\treturn;\n \t}\n-\n-\tcmd.opcode = inv->nsize_opcode;\n-\tarm_smmu_cmdq_build_cmd(&hw_cmd, &cmd);\n-\tarm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, hw_cmd);\n }\n \n /* Should be installed after arm_smmu_install_ste_for_dev() */\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 538380de7d48a0..16353596e08ad8 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -583,6 +583,21 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_sync(unsigned int cs,\n \treturn cmd;\n }\n \n+/*\n+ * TLBI commands - the non-sized variants just need opcode + asid/vmid.\n+ * For sized variants the caller sets up data[0] with the immutable fields\n+ * (opcode + asid/vmid) and the range loop fills in per-iteration fields.\n+ */\n+static inline struct arm_smmu_cmd\n+arm_smmu_make_cmd_tlbi(enum arm_smmu_cmdq_opcode op, u16 asid, u16 vmid)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(op);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, asid) |\n+\t\t FIELD_PREP(CMDQ_TLBI_0_VMID, vmid);\n+\treturn cmd;\n+}\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -643,26 +658,6 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_sync(unsigned int cs,\n #define MSI_IOVA_BASE\t\t\t0x8000000\n #define MSI_IOVA_LENGTH\t\t\t0x100000\n \n-struct arm_smmu_cmdq_ent {\n-\t/* Common fields */\n-\tu8\t\t\t\topcode;\n-\tbool\t\t\t\tsubstream_valid;\n-\n-\t/* Command-specific fields */\n-\tunion {\n-\t\tstruct {\n-\t\t\tu8\t\t\tnum;\n-\t\t\tu8\t\t\tscale;\n-\t\t\tu16\t\t\tasid;\n-\t\t\tu16\t\t\tvmid;\n-\t\t\tbool\t\t\tleaf;\n-\t\t\tu8\t\t\tttl;\n-\t\t\tu8\t\t\ttg;\n-\t\t\tu64\t\t\taddr;\n-\t\t} tlbi;\n-\t};\n-};\n-\n struct arm_smmu_ll_queue {\n \tunion {\n \t\tu64\t\t\tval;\n", "prefixes": [ "9/9" ] }