Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2231728/?format=api
{ "id": 2231728, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231728/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-27-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260501101505.3485916-27-peter.maydell@linaro.org>", "date": "2026-05-01T10:15:03", "name": "[PULL,26/28] hvf: arm: physical timer emulation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4498bd20f11c1ff7e08a045ff3a4524990bfa2c3", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-27-peter.maydell@linaro.org/mbox/", "series": [ { "id": 502437, "url": "http://patchwork.ozlabs.org/api/1.1/series/502437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502437", "date": "2026-05-01T10:14:41", "name": "[PULL,01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231728/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231728/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EkczOc64;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6RnN3TcLz1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 01 May 2026 20:18:00 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIkuQ-00047U-Qx; Fri, 01 May 2026 06:15:46 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuL-00044j-1n\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:41 -0400", "from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuJ-0000Hm-AG\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:40 -0400", "by mail-wm1-x32b.google.com with SMTP id\n 5b1f17b1804b1-488b0046078so14846445e9.1\n for <qemu-devel@nongnu.org>; Fri, 01 May 2026 03:15:38 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-48a8fede418sm12863335e9.6.2026.05.01.03.15.37\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 01 May 2026 03:15:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777630538; x=1778235338; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=JNEtBvOkPyY2VflHuwbXWSp3/7gfXfuP2T8jg+5DLbA=;\n b=EkczOc64KN2Htjz+XLRDKhu8L9M/jkJ3wvkpqOUumaQ3aEYv+4aPk8YnPvmdED3LxZ\n FwI/yczuyAI+DoYhZafbB18XA54paNjhP/kLFyiT3KenIJlfiZFs3kALSpGbETgMAwTk\n kjYqbSJnOgwRXbjXIMMm6rPwQVdhao2FP9fVNicF8t1e5KhyErL8gBGpXELz6hC2Vble\n 38HIskjwd62szXus35kHe9Ny8SOVjfKHm2bkQ0pTieNQSn4SiJp/fuDCi88N2UY7RMfn\n vChWKJuL1612UZzfHtzvpM5sBWU88LKdMKiHplquNa5TD5UdSgTPdvTYWa6sZO+x/GaX\n 4+EA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777630538; x=1778235338;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=JNEtBvOkPyY2VflHuwbXWSp3/7gfXfuP2T8jg+5DLbA=;\n b=UpqI64NaWCPp3yIGfNsE29iWPJ9UpKkyhQ5iw6Y34zvL96fvvltMntcQ+OQ5iTeDzZ\n RJObcRnUSxOc0uqlYco0zZcZrWKKYObkBBfg3hWI3Xuk4S91TvOVsZQKzOYlzu+lHAuQ\n 40KuV8V+hebgJvNv2xWlrDUMzB+m5nupBM4j3JOGvPQbalvgBb4kCjyV1yTVwLBABKZR\n dIyzXUs/Gazkc8Msp+LV9H0jJm6y4M0eWy2N4iGYZbsELANsRIfP578CZMqiNKq+ew7Z\n Lkf+4MET7Zo9wP0dwx0fcbru9Lphp+LZU0BELlSSelS/ydY82LYVAAnR+4TBKWNW0VKM\n uKag==", "X-Gm-Message-State": "AOJu0YwJfr7PxL5daDZr3pnFiOkVA3DdL82rpwcbQMojBw25ki1Rxxmn\n QtHS9S7spywSxfCuRuRKb7SHMX2lPo75eMGkSXDqAwB3ohd3GySJnW7zvuclwdKOmeW+DzhnDdD\n ZcD15", "X-Gm-Gg": "AeBDiess9JWusPOGBbFay9tHgoBqZzXiUK8LcOoJgEMGTi6PT7zJKHchQw2J1O78FR5\n bTAGwi8FQc6bN5SZPV4Gz2inCA2Qefc0D/vZF7Z9EMhtiQC72kDdPiL3VefKAJ7PzH+UDmW+W36\n jaV3cVVBFZkF/9pthWQYZt12i1Oh2IAAleAVquhsIXtc0puMj60O670II9SHr4EjwX2333buF6i\n P67cuhStJogfhv2ODb4TnbnhiumcGV8tSwDBJnbywIg66hU/OLDKV4msSEooB8JSGi3O8qpMDpZ\n OzhCCJ8O4PJQfM7rWuMLjXwJjMlpJtWJg/DZEP9AG23pr82jrdJ1dRKLFw/4iHedggJHGavJzZ2\n AArEzDvj2XpkJ8LuKwh17ggRE4K0i60i2V8JKxm3b+kbadc/TsO9SN8m9saZSuCulkK6OoAMLeG\n 9d0rj1OUT6HkzCLb6k3lHrlmN0hINeetcDSsyjioW1U24MqcnAy+Xq4yaa0YrD3wFYJ5n/JFxqt\n 0rOBKAJXLEUBsh24O+hUi44aPYYF3ubl2bX3CCaKw==", "X-Received": "by 2002:a05:600c:1f8f:b0:48a:8905:a500 with SMTP id\n 5b1f17b1804b1-48a8eb74345mr34514715e9.12.1777630537886;\n Fri, 01 May 2026 03:15:37 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 26/28] hvf: arm: physical timer emulation", "Date": "Fri, 1 May 2026 11:15:03 +0100", "Message-ID": "<20260501101505.3485916-27-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "References": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nEnable this through leveraging TCG's physical timer emulation.\nThis allows nested virtualisation to work with a kernel-irqchip=off + GICv2.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nMessage-id: 20260429190532.26538-14-mohamed@unpredictable.fr\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/hvf/hvf.c | 28 +++++++++++++++++++---------\n 1 file changed, 19 insertions(+), 9 deletions(-)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 6062e08c49..2252b96f83 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -189,7 +189,9 @@ void hvf_arm_init_debug(void)\n #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)\n #define SYSREG_LORC_EL1 SYSREG(3, 0, 10, 4, 3)\n #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)\n+#define SYSREG_CNTP_TVAL_EL0 SYSREG(3, 3, 14, 2, 0)\n #define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1)\n+#define SYSREG_CNTP_CVAL_EL0 SYSREG(3, 3, 14, 2, 2)\n #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)\n #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)\n #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)\n@@ -1719,9 +1721,15 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)\n \n switch (reg) {\n case SYSREG_CNTPCT_EL0:\n- *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /\n- gt_cntfrq_period_ns(arm_cpu);\n- return 0;\n+ case SYSREG_CNTP_CTL_EL0:\n+ case SYSREG_CNTP_CVAL_EL0:\n+ case SYSREG_CNTP_TVAL_EL0:\n+ assert(!hvf_irqchip_in_kernel());\n+ /* Call the TCG sysreg handler. */\n+ if (hvf_sysreg_read_cp(cpu, \"PTimer\", reg, val)) {\n+ return 0;\n+ }\n+ break;\n case SYSREG_OSLSR_EL1:\n *val = env->cp15.oslsr_el1;\n return 0;\n@@ -2015,12 +2023,14 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)\n env->cp15.oslsr_el1 = val & 1;\n return 0;\n case SYSREG_CNTP_CTL_EL0:\n- /*\n- * Guests should not rely on the physical counter, but macOS emits\n- * disable writes to it. Let it do so, but ignore the requests.\n- */\n- qemu_log_mask(LOG_UNIMP, \"Unsupported write to CNTP_CTL_EL0\\n\");\n- return 0;\n+ case SYSREG_CNTP_CVAL_EL0:\n+ case SYSREG_CNTP_TVAL_EL0:\n+ assert(!hvf_irqchip_in_kernel());\n+ /* Call the TCG sysreg handler. */\n+ if (hvf_sysreg_write_cp(cpu, \"PTimer\", reg, val)) {\n+ return 0;\n+ }\n+ break;\n case SYSREG_OSDLR_EL1:\n /* Dummy register */\n return 0;\n", "prefixes": [ "PULL", "26/28" ] }